EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 33

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
Table 1–32. Cyclone III Devices FPGA Sampling Window (SW) Requirement – Read Side
© January 2010 Altera Corporation
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
Note to
(1) Column I/Os refer to top and bottom I/Os. Row I/Os refer to right and left I/Os. Wraparound mode refers to the combination of column and row
I/Os.
Memory Standard
Table
1–32:
f
External Memory Interface Specifications
Cyclone III devices support external memory interfaces up to 200 MHz. The external
memory interfaces for Cyclone III devices are auto-calibrating and easy to implement.
For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to
Table 1–32
Literature: External Memory
Setup
1050
1090
580
585
785
705
675
900
785
800
765
745
945
805
880
lists the FPGA sampling window specifications for Cyclone III devices.
Column I/Os
1030
Hold
550
535
735
650
620
845
720
740
990
710
690
890
745
820
C6
C7
C8
A7
I7
Interfaces.
Setup
1065
1020
1105
690
700
805
770
795
910
930
915
855
880
955
955
Row I/Os
1005
1045
Hold
640
650
755
715
740
855
870
855
800
825
900
960
935
(Note 1)
Cyclone III Device Handbook, Volume 2
Setup
1085
1115
1185
1210
1040
1000
1130
1145
1220
1250
850
870
905
985
970
Wraparound Mode
1030
1055
1125
1150
1075
1085
1160
1190
Hold
800
820
855
930
915
985
945
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