EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 66

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

2–22
Table 2–32. FPGA Sampling Window (SW) Requirement—Read Side
Cyclone III Device Handbook, Volume 2
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
DDR2 SDRAM
DDR SDRAM
QDRII SRAM
Note to
(1) Column I/Os refer to top and bottom I/Os. Row I/Os refer to right and left I/Os. Wraparound mode refers to the combination of column and row
I/Os.
Memory Standard
Table
2–32:
f
Table 2–31. Cyclone III LS Devices LVDS Receiver Timing Specifications
External Memory Interface Specifications
Cyclone III LS devices support external memory interfaces up to 200 MHz. The
external memory interfaces for Cyclone III LS devices are auto-calibrating and easy to
implement.
Table 2–32
Cyclone III LS devices and are useful when performing memory interface timing
analysis.
For more information about external memory system specifications, refer to the
External Memory Interface
(Part 2 of 2) (Preliminary)
Input jitter
tolerance
t
Notes to
(1) True LVDS receiver is supported at all banks.
(2) t
LOCK
(2)
LOC K
Symbol
Table
is the time required for the PLL to lock from the end of device configuration.
and
Setup
1050
705
675
900
785
800
765
745
945
2–31:
Column I/Os (ps)
Table 2–33
Modes
—
—
Hold
650
620
845
720
740
990
710
690
890
Handbook.
list the external memory interface specifications for
C7
C8
I7
Min
—
—
Setup
1065
C7 and I7
770
795
910
930
915
855
880
955
(Note 1)
Row I/Os (ps)
Max
500
1
(Preliminary)
Hold
1005
715
740
855
870
855
800
825
900
Chapter 2: Cyclone III LS Device Data Sheet
© December 2009 Altera Corporation
Min
—
—
Wraparound Mode (ps)
(Note 1)
Setup
1185
1210
1040
1000
1085
1115
1130
C8
985
970
Switching Characteristics
Max
550
1
1030
1055
1125
1150
1075
Hold
930
915
985
945
Unit
ps
ps