EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 31

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
© January 2010 Altera Corporation
Table 1–29. Cyclone III Devices True LVDS Transmitter Timing Specifications
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications
of 2)
f
clock frequency)
HSIODR
t
TCCS
Output jitter
(peak to peak)
t
Notes to
(1) True LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6).
(2) t
f
frequency)
HSIODR
t
HSC LK
DUTY
LOCK
HSC LK
DUTY
(2)
Symbol
Symbol
LOC K
(input clock
(input
Table
is the time required for the PLL to lock from the end of device configuration.
1–29:
Modes
Modes
×10
×10
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
Min
100
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
10
10
10
10
10
10
80
70
40
20
10
45
C6
C6
402.5
402.5
Max
420
420
420
420
420
420
840
840
840
840
840
420
200
500
Max
320
320
320
320
320
640
640
640
640
640
55
55
1
Min
100
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
10
10
10
10
10
10
80
70
40
20
10
45
C7, I7
C7, I7
402.5
402.5
402.5
402.5
Max
370
370
370
370
370
740
740
740
740
740
200
500
Max
320
320
320
320
320
640
640
640
640
640
55
55
1
Cyclone III Device Handbook, Volume 2
Min
100
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
10
10
10
10
10
10
80
70
40
20
10
45
C8, A7
(Note 1)
C8, A7
(Note 1)
402.5
402.5
402.5
402.5
Max
320
320
320
320
320
640
640
640
640
640
200
550
Max
275
275
275
275
275
550
550
550
550
550
55
55
1
(Part 1
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
%
ps
ps
%
1–21