EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 29

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
Table 1–26. Cyclone III Devices RSDS Transmitter Timing Specifications
Table 1–27. Cyclone III Devices Emulated RSDS_E_1R Transmitter Timing Specifications
© January 2010 Altera Corporation
Device operation in
Mbps
t
TCCS
Output jitter
(peak to peak)
t
t
t
Notes to
(1) Applicable for true RSDS and emulated RSDS_E_3R transmitter.
(2) True RSDS transmitter is only supported at output pin of Row I/O (Banks 1, 2, 5, and 6). Emulated RSDS transmitter is supported at the output
(3) t
f
clock
frequency)
Device
operation in
Mbps
t
TCCS
Output jitter
(peak to
peak)
DUTY
RISE
FALL
LOCK
HSC LK
DUTY
Symbol
(3)
pin of all I/O banks.
LOC K
(input
Symbol
Table
is the time required for the PLL to lock from the end of device configuration.
1–26:
Modes
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
20 – 80%, C
20 – 80%, C
Modes
×10
×8
×7
×4
×2
×1
—
—
—
—
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
LOA D
LOA D
= 5 pF
= 5 pF
Typ
C6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min
100
80
70
40
20
10
45
—
—
—
—
—
Max
170
170
170
170
170
170
170
200
500
85
85
85
85
85
55
500
500
Typ
C6
—
—
—
—
—
—
—
—
—
—
Min
100
Max
360
360
360
360
360
360
200
500
10
10
10
10
10
10
80
70
40
20
10
45
—
—
55
—
—
1
C7, I7
Min
100
80
70
40
20
10
45
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(Note
C7, I7
500
500
Typ
—
—
—
—
—
—
—
—
—
—
Max
170
170
170
170
170
170
170
200
500
85
85
85
85
85
55
1),
Max
(2)
311
311
311
311
311
311
200
500
55
—
—
1
(Note 1)
Min
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
Cyclone III Device Handbook, Volume 2
(Part 2 of 2)
Min
100
80
70
40
20
10
45
—
—
—
—
—
C8, A7
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(Part 1 of 2)
C8, A7
500
500
Typ
—
—
—
—
—
—
—
—
—
—
Max
170
170
170
170
170
170
170
200
550
85
85
85
85
85
55
Max
311
311
311
311
311
311
200
550
55
—
—
1
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
ps
ps
Unit
ms
%
ps
ps
ps
ps
1–19