EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 70

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

2–26
Glossary
Table 2–39. Glossary (Part 1 of 5)
Cyclone III Device Handbook, Volume 2
Letter
M
D
G
H
N
O
A
B
C
E
F
K
L
I
J
f
GCLK
GCLK PLL
HSIODR
Input Waveforms
for the SSTL
Differential I/O
Standard
JTAG Waveform
HS CLK
Term
—
—
—
—
—
—
—
—
—
—
Table 2–39
V
Captured
High-speed I/O Block: High-speed receiver and transmitter input and output clock frequency.
Input pin directly to the global clock network.
High-speed I/O Block: Maximum and minimum LVDS data transfer rate (HSIODR = 1/TUI).
Input pin to the global clock network through the PLL.
SWING
Driven
Signal
Signal
to be
to be
TMS
TDO
TCK
TDI
lists the glossary for this chapter.
t
JCH
t
t
JSZX
JPZX
t
JCP
t
JSSU
t
JCL
t
JSH
t
t
JPCO
JSCO
t
t
JPSU_TDI
JPSU_TMS
Definitions
—
—
—
—
—
—
—
—
—
—
t
Chapter 2: Cyclone III LS Device Data Sheet
t
JSXZ
JPH
© December 2009 Altera Corporation
t
JPXZ
V
V
V
REF
IH
IL
Glossary