EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 62

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

2–18
Table 2–26. Cyclone III LS Devices RSDS Transmitter Timing Specification
Cyclone III Device Handbook, Volume 2
f
(input clock
frequency)
Device operation
in Mbps
t
TCCS
Output jitter
(peak to peak)
t
t
t
Notes to
(1) Applicable for true RSDS and Emulated RSDS with three-resistor network transmitters.
(2) True RSDS transmitter is only supported at the output pin of the Row I/O (Banks 1, 2, 5, and 6). Emulated RSDS with three-resistor network
(3) t
HSC LK
DUTY
RISE
FALL
LOC K
(3)
transmitter is supported at the output pin of all I/O banks.
LOC K
Symbol
Table
is the time required for the PLL to lock from the end of device configuration.
2–26:
Table 2–27. Cyclone III LS Devices Emulated RSDS with One-Resistor Network Transmitter Timing
Specifications
C
C
f
clock
frequency)
20 – 80%,
20 – 80%,
HSC LK
LOAD
LOAD
Modes
Symbol
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
—
= 5 pF
= 5 pF
(input
(Note 1)
Min
100
Modes
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
—
—
×10
×8
×7
×4
×2
×1
(Part 1 of 2) (Preliminary)
C7 and I7
500
500
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min
10
10
10
10
10
10
C7 and I7
155.5
155.5
155.5
155.5
155.5
Max
311
311
311
311
311
311
311
200
500
55
—
—
1
Typ
—
—
—
—
—
—
(Note
Max
170
Min
85
85
85
85
85
100
10
10
10
10
10
10
80
70
40
20
10
45
—
—
—
—
—
1),
(2)
Chapter 2: Cyclone III LS Device Data Sheet
Min
10
10
10
10
10
10
(Preliminary)
© December 2009 Altera Corporation
500
500
Typ
C8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
C8
—
—
—
—
—
—
155.5
155.5
155.5
155.5
155.5
Switching Characteristics
Max
311
311
311
311
311
311
311
200
550
55
—
—
1
Max
170
85
85
85
85
85
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ps
ps
ps
ps
%