EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 63

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

Chapter 2: Cyclone III LS Device Data Sheet
Switching Characteristics
Table 2–28. Cyclone III LS Devices Mini-LVDS Transmitter Timing Specification
© December 2009
f
frequency)
Device operation
in Mbps
t
TCCS
HSC LK
DUTY
Symbol
(input clock
Altera Corporation
Table 2–27. Cyclone III LS Devices Emulated RSDS with One-Resistor Network Transmitter Timing
Specifications
Device
operation in
Mbps
t
TCCS
Output jitter
(peak to
peak)
t
t
t
Notes to
(1) Emulated RSDS with one-resistor network transmitter is supported at the output pin of all I/O banks.
(2) t
DUTY
RISE
FALL
LOCK
Modes
Symbol
(2)
×10
×10
LOC K
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
Table
is the time required for the PLL to lock from the end of device configuration.
2–27:
(Note 1)
20 – 80%,
C
20 – 80%,
C
LOAD
LOAD
Modes
= 5 pF
= 5 pF
×10
Min
100
×8
×7
×4
×2
×1
—
—
—
—
10
10
10
10
10
10
80
70
40
20
10
45
—
(Part 2 of 2) (Preliminary)
C7 and I7
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min
100
80
70
40
20
10
45
—
—
—
—
—
155.5
155.5
155.5
155.5
155.5
C7 and I7
Max
311
311
311
311
311
311
311
200
55
500
500
Typ
—
—
—
—
—
—
—
—
—
—
Max
Min
170
170
170
170
170
170
200
500
100
55
—
—
10
10
10
10
10
10
80
70
40
20
10
45
—
1
(Note 1)
Min
100
80
70
40
20
10
45
—
—
—
—
—
,
(2)
C8
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cyclone III Device Handbook, Volume 2
(Part 1 of 2) (Preliminary)
500
500
Typ
C8
—
—
—
—
—
—
—
—
—
—
155.5
155.5
155.5
155.5
155.5
Max
311
311
311
311
311
311
311
200
55
Max
170
170
170
170
170
170
200
550
55
—
—
1
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
ps
%
Unit
ms
ps
ps
ps
ps
%
2–19