EP3C55F484C8N Altera, EP3C55F484C8N Datasheet - Page 24

• Manufacturer Part Number: EP3C55F484C8N
• Description: IC CYCLONE III FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484C8N

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 55856
• # I/os (max): 327
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 55856
• Ram Bits: 2396160
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 3491
• Family Type: Cyclone III
• No. Of I/o's: 327
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2510

1–14
Table 1–18. Cyclone III Devices Differential I/O Standard Specifications
Power Consumption
Cyclone III Device Handbook, Volume 2
mini-LVDS
(Row I/Os)
(6)
mini-LVDS
(Column
I/Os)
RSDS
(Row
I/Os)(6)
RSDS
(Column
I/Os)
PPDS
(Row I/Os)
(6)
PPDS
(Column
I/Os)
Notes to
(1) For an explanation of terms used in
(2) V
(3) R
(4) LVPECL input standard is only supported at clock input. Output standard is not supported.
(5) No fixed V
(6) Mini-LVDS, RSDS, and PPDS standards are only supported at the output pins for Cyclone III devices.
Standard
I/O
IN
(6)
(6)
(6)
L
®
®
range: 90 ≤ R
range: 0 V ≤ V
Table
IN
f
1–18:
, V
2.375
2.375
2.375
2.375
2.375
2.375
Min
OD
L
, and V
IN
≤ 110 Ω.
≤ 1.85 V.
V
C CIO
You can use the following methods to estimate power for a design:
■
■
The interactive Excel-based EPE is used prior to designing the device to get a
magnitude estimate of the device power. The Quartus II PowerPlay power analyzer
provides better quality estimates based on the specifics of the design after place-and-
route is complete. The PowerPlay power analyzer can apply a combination of user-
entered, simulation-derived, and estimated signal activities which, combined with
detailed circuit models, can yield very accurate power estimates.
For more information about power estimation tools, refer to the
User Guide
Handbook.
Typ
2.5
2.5
2.5
2.5
2.5
2.5
OS
(V)
specifications for BLVDS. They are dependent on the system topology.
the Excel-based EPE.
the Quartus II PowerPlay power analyzer feature.
2.625
2.625
2.625
2.625
2.625
2.625
Max
Table
and the
Min
—
—
—
—
—
—
1–18, refer to
V
ID
(mV)
Max
PowerPlay Power Analysis
—
—
—
—
—
—
“Transmitter Output Waveform”
Min
—
—
—
—
—
—
V
Condition
IcM
(V)
—
—
—
—
—
—
(2)
(Note 1)
chapter in volume 3 of the Quartus II
in
Max Min Typ
“Glossary” on page
—
—
—
—
—
—
(Part 2 of 2)
300
300
100 200
100 200
100 200
100 200
Chapter 1: Cyclone III Device Data Sheet
V
O D
© January 2010 Altera Corporation
(mV)
—
—
1–27.
Early Power Estimator
(3)
Max
600
600
600
600
600
600
Electrical Characteristics
Min
1.0
1.0
0.5
0.5
0.5
0.5
V
O S
Typ
(V)
1.2
1.2
1.2
1.2
1.2
1.2
(3)
Max
1.4
1.4
1.5
1.5
1.4
1.4