EP4CE55F23I8L Altera, EP4CE55F23I8L Datasheet - Page 231
EP4CE55F23I8L
Manufacturer Part Number
EP4CE55F23I8L
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F23I8L
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
EP4CE55F23I8LN
Manufacturer:
ALTERA
Quantity:
239
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Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
Table 8–18. Dedicated Configuration Pins on the Cyclone IV Device (Part 3 of 4)
© December 2010 Altera Corporation
DCLK
DATA[0]
DATA[1]/
ASDO
Pin Name
Mode
User
N/A
I/O
I/O
Configuration
PS, FPP, AS,
PS, FPP, AS,
FPP, AS, AP
Scheme
AP
AP
(1)
(1)
(1)
Output (AS).
Bidirectional
Input (FPP).
Bidirectional
Output (AS,
Input (PS,
Input (PS,
FPP, AS).
Pin Type
(AP)
(AP)
AP)
FPP).
(1)
(1)
(1)
In PS and FPP configuration, DCLK is the clock input used to
clock data from an external source into the target Cyclone IV
device. Data is latched into the device on the rising edge of
DCLK.
In AS mode, DCLK is an output from the Cyclone IV device that
provides timing for the configuration interface. It has an internal
pull-up resistor (typically 25 k) that is always active.
In AP mode, DCLK is an output from the Cyclone IV E device
that provides timing for the configuration interface.
In AS or AP configuration schemes, this pin is driven into an
inactive state after configuration completes. Alternatively, in
active schemes, you can use this pin as a user I/O during user
mode. In PS or FPP schemes that use a control host, you must
drive DCLK either high or low, whichever is more convenient. In
passive schemes, you cannot use DCLK as a user I/O in user
mode. Toggling this pin after configuration does not affect the
configured device.
Data input. In serial configuration modes, bit-wide configuration
data is presented to the target Cyclone IV device on the
DATA[0] pin.
In AS mode, DATA[0] has an internal pull-up resistor that is
always active. After AS configuration, DATA[0] is a dedicated
input pin with optional user control.
After PS or FPP configuration, DATA[0] is available as a user
I/O pin. The state of this pin depends on the Dual-Purpose Pin
settings.
After AP configuration, DATA[0]is a dedicated bidirectional pin
with optional user control.
The DATA[1] pin functions as the ASDO pin in AS mode. Data
input in non-AS mode. Control signal from the Cyclone IV device
to the serial configuration device in AS mode used to read out
configuration data.
In AS mode, DATA[1] has an internal pull-up resistor that is
always active. After AS configuration, DATA[1] is a dedicated
output pin with optional user control.
In a PS configuration scheme, DATA[1] functions as a user I/O
pin during configuration, which means it is tri-stated.
After FPP configuration, DATA[1] is available as a user I/O pin
and the state of this pin depends on the Dual-Purpose Pin
settings.
In an AP configuration scheme, for Cyclone IV E devices only,
the byte-wide or word-wide configuration data is presented to
the target Cyclone IV E device on DATA[7..0] or
DATA[15..0], respectively. After AP configuration,
DATA[1]is a dedicated bidirectional pin with optional user
control.
(1)
Description
(1)
Cyclone IV Device Handbook, Volume 1
(1)
8–65
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