EP4CE55F23I8L Altera, EP4CE55F23I8L Datasheet - Page 346
EP4CE55F23I8L
Manufacturer Part Number
EP4CE55F23I8L
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F23I8L
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE55F23I8LN
Manufacturer:
ALTERA
Quantity:
239
- EP4CGX15BN11C8N PDF datasheet
- EP4CGX15BN11C8N PDF datasheet #2
- EP4CGX15BN11C8N PDF datasheet #3
- EP4CGX15BN11C8N PDF datasheet #4
- Current page: 346 of 478
- Download datasheet (13Mb)
1–66
Figure 1–65. Deskew FIFO–Lane Skew at the Receiver Input
Cyclone IV Device Handbook, Volume 2
Lane 0
Lane 2
K
Lane 1
Lane 3
K
K
Lane 0
Lane 1
Lane 2
Lane 3
R
K
K
K
■
■
■
Figure 1–65
/A/ code group to align the channels.
Lane Synchronization
In XAUI mode, the word aligner is configured in automatic synchronization state
machine mode that is compliant to the PCS synchronization state diagram specified in
clause 48 of the IEEE P802.3ae specification.
machine parameters that implements the lane synchronization in XAUI mode.
Table 1–23. Synchronization State Machine Parameters
Number of valid synchronization (/K28.5/) code groups received to achieve
synchronization
Number of erroneous code groups received to lose synchronization
Number of continuous good code groups received to reduce the error count by
one
Note to
(1) The word aligner supports 7-bit and 10-bit pattern lengths in XAUI mode.
K
K
K
K
Channel alignment is acquired if three additional aligned ||A|| columns are
observed at the output of the deskew FIFOs of the four channels after alignment of
the first ||A|| column.
Channel alignment is indicated by the assertion of rx_channelaligned signal.
After acquiring channel alignment, if four misaligned ||A|| columns are seen at
the output of the deskew FIFOs in all four channels with no aligned ||A||
columns in between, the rx_channelaligned signal is deasserted, indicating
loss of channel alignment.
R
A
K
K
K
K
K
K
Table
K
R
A
R
1–23:
R
R
R
R
shows lane skew at the receiver input and how the deskew FIFO uses the
/A/ column
R
A
K
A
A
A
A
A
R
R
K
K
K
K
K
K
K
R
R
R
R
R
R
R
Parameter
K
R
K
R
R
R
R
R
R
K
K
K
K
K
K
K
K
K
R
K
K
K
K
K
Table 1–23
R
R
R
K
Chapter 1: Cyclone IV Transceivers Architecture
(Note 1)
R
R
R
R
K
R
K
K
K
K
K
lists the synchronization state
R
R
© December 2010 Altera Corporation
R
R
R
R
Transceiver Functional Modes
Lanes skew at
receiver input
Lanes are deskewed by lining
up the “Align”/A/ code groups
Value
4
4
4
Related parts for EP4CE55F23I8L
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: