EP4CE55F23I8L Altera, EP4CE55F23I8L Datasheet - Page 297
EP4CE55F23I8L
Manufacturer Part Number
EP4CE55F23I8L
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F23I8L
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE55F23I8LN
Manufacturer:
ALTERA
Quantity:
239
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Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath
Figure 1–18. Word Aligner Configured in Bit-Slip Mode
© December 2010 Altera Corporation
rx_patterndetect
rx_dataout[7..0]
rx_datain7..0]
rx_clkout
rx_bitslip
1
1
Bit-Slip Mode
In bit-slip mode, the rx_bitslip port controls the word aligner operation. At every
rising edge of the rx_bitslip signal, the bit-slip circuitry slips one bit into the
received data stream, effectively shifting the word boundary by one bit. When the
received data after bit-slipping matches the programmed word alignment pattern, the
rx_patterndetect signal is driven high for one parallel clock cycle.
You can implement a bit-slip controller in the user logic that monitors either the
rx_patterndetect signal or the receiver data output (rx_dataout), and controls
the rx_bitslip port to achieve word alignment.
Figure 1–18
this example, consider that 8'b11110000 is received back-to-back and
16'b0000111100011110 is specified as the word alignment pattern. A rising edge on the
rx_bitslip signal at time n + 1 slips a single bit 0 at the MSB position, forcing the
rx_dataout to 8'b01111000. Another rising edge on the rx_bitslip signal at time n
+ 5 forces rx_dataout to 8'b00111100. Another rising edge on the rx_bitslip signal
at time n + 9 forces rx_dataout to 8'b00011110. Another rising edge on the
rx_bitslip signal at time n + 13 forces the rx_dataout to 8'b00001111. At this
instance, rx_dataout in cycles n + 12 and n + 13 is 8'b00011110 and 8'b00001111,
respectively, which matches the specified 16-bit alignment pattern
16'b0000111100011110. This results in the assertion of the rx_patterndetect signal.
Automatic Synchronization State Machine Mode
In automatic synchronization state machine mode, the word aligner achieves
synchronization after receiving a specific number of synchronization code groups,
and falls out of synchronization after receiving a specific number of erroneous code
groups. This mode provides hysteresis during link synchronization, which is required
by protocols such as PCIe, GbE, XAUI, and Serial RapidIO.
This mode is only supported using the 8B/10B encoded data with 10-bit input to the
word aligner.
11110000
n
shows an example of the word aligner configured in bit-slip mode. For
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7
01111000
11110000
00111100
n + 8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14
00011110
Cyclone IV Device Handbook, Volume 2
00001111
1–17
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