EP4CE55F23I8L Altera, EP4CE55F23I8L Datasheet - Page 362
EP4CE55F23I8L
Manufacturer Part Number
EP4CE55F23I8L
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F23I8L
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE55F23I8LN
Manufacturer:
ALTERA
Quantity:
239
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1–82
Table 1–27. Receiver Ports in ALTGX Megafunction for Cyclone IV GX (Part 3 of 3)
Cyclone IV Device Handbook, Volume 2
RX PCS
RX PMA
Block
rx_coreclk
rx_phase_comp_
fifo_error
rx_bitslipboun
daryselectout
rx_datain
rx_freqlocked
rx_locktodata
rx_locktoref
clk
rx_signalde
tect
rx_recovclkout
Port Name
Output
Output Clock signal
Output
Output Asynchronous signal.
Output Asynchronous signal
Output Asynchronous signal
Output Asynchronous signal
Output Asynchronous signal
Output Clock signal
Input/
Input
Synchronous to tx_clkout (non-
bonded modes) or coreclkout
(bonded modes)
N/A
Clock Domain
Chapter 1: Cyclone IV Transceivers Architecture
Optional read clock port for the RX phase compensation
FIFO.
RX phase compensation FIFO full or empty indicator.
■
Indicate the number of bits slipped in the word aligner
configured in manual alignment mode.
■
Receiver serial data input port.
Receiver CDR lock state indicator
■
■
Receiver CDR LTD state control signal
■
■
Receiver CDR LTR state control signal.
■
Signal threshold detect indicator.
■
■
CDR low-speed recovered clock
■
A high level indicates FIFO is either full or empty.
Values range from 0 to 9.
A high level indicates the CDR is in LTD state.
A low level indicates the CDR is in LTR state.
A high level forces the CDR to LTD state
When deasserted, the receiver CDR lock state depends
on the rx_locktorefclk signal level.
The rx_locktorefclk and rx_locktodata
signals control whether the receiver CDR states as
follows:
[rx_locktodata:rx_locktorefclk]
Available in Basic mode when 8B/10B encoder/decoder
is used, and in PIPE mode.
A high level indicates that the signal present at the
receiver input buffer is above the programmed signal
detection threshold value.
Only available in the GIGE mode for applications such as
Synchronous Ethernet.
2'b00—receiver CDR is in automatic lock mode
2b'01—receiver CDR is in manual lock mode (LTR
state)
2b'1x—receiver CDR is in manual lock mode (LTD
state)
© December 2010 Altera Corporation
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