EP4CE55F23I8L Altera, EP4CE55F23I8L Datasheet - Page 420
EP4CE55F23I8L
Manufacturer Part Number
EP4CE55F23I8L
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F23I8L
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Part Number:
EP4CE55F23I8LN
Manufacturer:
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3–30
Figure 3–14. Option 2 for Receiver Core Clocking (Channel Reconfiguration Mode)
Note to
(1) Assuming channel 2 and 3 are running at the same data rate with rate matcher enabled and are reconfigured to another Basic or Protocol functional
Cyclone IV Device Handbook, Volume 2
mode with rate matching enabled.
Figure
3–14:
tx_clkout[0]
tx_clkout[1]
tx_clkout[2]
FPGA Fabric
Figure 3–14
channels of a transceiver block.
Option 3: Use the Respective Channel Receiver Core Clocks
■
■
Low-speed parallel clock
High-speed serial clock generated by the MPLL
Enable this option if you want the individual channel’s rx_clkout signal to
provide the read clock to its respective Receive Phase Compensation FIFO.
This option is typically enabled when the channel is reconfigured from a Basic or
Protocol configuration with or without rate matching to another Basic or Protocol
configuration with or without rate matching.
shows the respective tx_clkout of each channel clocking the respective
Transceiver Block
RX0
RX1
RX2 (1)
RX3 (1)
TX0
TX1
TX2 (1)
TX3 (1)
Chapter 3: Cyclone IV Dynamic Reconfiguration
© December 2010 Altera Corporation
MPLL
Dynamic Reconfiguration Modes
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