EP4CE55F23I8L Altera, EP4CE55F23I8L Datasheet - Page 381
EP4CE55F23I8L
Manufacturer Part Number
EP4CE55F23I8L
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F23I8L
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Manufacturer
Quantity
Price
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Part Number:
EP4CE55F23I8LN
Manufacturer:
ALTERA
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239
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Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
© December 2010 Altera Corporation
As shown in
manual lock mode:
1. After power up, assert pll_areset for a minimum period of 1 s (the time
2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and
3. After the multipurpose PLL locks, as indicated by the pll_locked signal going
4. Wait for at least t
5. Deassert rx_digitalreset at least t
between markers 1 and 2).
rx_locktorefclk signals asserted and the rx_locktodata signal deasserted
during this time period. After you deassert the pll_areset signal, the
multipurpose PLL starts locking to the transmitter input reference clock.
high (marker 3), deassert tx_digitalreset. For receiver operation, after
deassertion of busy signal, wait for two parallel clock cycles to deassert the
rx_analogreset signal.
rx_locktorefclk signal. At the same time, assert the rx_locktodata signal
(marker 7). At this point, the receiver CDR enters lock-to-data mode and the
receiver CDR starts locking to the received data.
after asserting the rx_locktodata signal. At this point, the transmitter and
receiver are ready for data traffic.
Figure
2–9, perform the following reset procedure for the receiver in
LTR_LTD_Manual
(the time between markers 6 and 7), then deassert the
LTD_Manual
(the time between markers 7 and 8)
Cyclone IV Device Handbook, Volume 2
2–15
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