EP4CE55F23I8L Altera, EP4CE55F23I8L Datasheet - Page 300
EP4CE55F23I8L
Manufacturer Part Number
EP4CE55F23I8L
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F23I8L
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Quantity
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Company:
Part Number:
EP4CE55F23I8LN
Manufacturer:
ALTERA
Quantity:
239
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1–20
Deskew FIFO
Cyclone IV Device Handbook, Volume 2
Figure 1–20. Receiver Bit Reversal
Note to
(1) The rx_revbitordwa port is dynamic and is only available when the word aligner is configured in bit-slip mode.
■
This module is only available when used for the XAUI protocol and is used to align all
four channels to meet the maximum skew requirement of 40 UI (12.8 ns) as seen at the
receiver of the four lanes. The deskew operation is compliant to the PCS deskew state
machine diagram specified in clause 48 of the IEEE P802.3ae specification.
The deskew circuitry consists of a 16-word deep deskew FIFO in each of the four
channels, and control logics in the central control unit of the transceiver block that
controls the deskew FIFO write and read operations in each channel.
For details about the deskew FIFO operations for channel deskewing, refer to
Mode” on page
1
Receiver bit-slip indicator—provides the number of bits slipped in the word
aligner for synchronization with rx_bitslipboundaryselectout signal. For
usage details, refer to
Figure
When using the receiver bit reversal feature to receive MSB-to-LSB
transmission, reversal of the word alignment pattern is required.
1–20:
1–61.
Output of word aligner
before RX bit reversal
“Receive Bit-Slip Indication” on page
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
(Note 1)
rx_revbitordwa (1) = HIGH
Output of word aligner
after RX bit reversal
Chapter 1: Cyclone IV Transceivers Architecture
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
© December 2010 Altera Corporation
1–70.
Receiver Channel Datapath
“XAUI
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