EP4CE55F23I8L Altera, EP4CE55F23I8L Datasheet - Page 51
EP4CE55F23I8L
Manufacturer Part Number
EP4CE55F23I8L
Description
IC CYCLONE IV FPGA 55K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F23I8L
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
0.97 V ~ 1.03 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Manufacturer
Quantity
Price
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Part Number:
EP4CE55F23I8LN
Manufacturer:
ALTERA
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239
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Chapter 3: Memory Blocks in Cyclone IV Devices
Design Considerations
Read or Write Clock Mode
Single-Clock Mode
Design Considerations
Read-During-Write Operations
© November 2009 Altera Corporation
Cyclone IV devices M9K memory blocks can implement read or write clock mode for
FIFO and simple dual-port memories. In this mode, a write clock controls the data
inputs, write address, and wren registers. Similarly, a read clock controls the data
outputs, read address, and rden registers. M9K memory blocks support independent
clock enables for both the read and write clocks.
When using read or write mode, if you perform a simultaneous read or write to the
same address location, the output read data is unknown. If you require the output
data to be a known value, use either single-clock mode, input clock mode, or output
clock mode and choose the appropriate read-during-write behavior in the
MegaWizard Plug-In Manager.
Cyclone IV devices M9K memory blocks can implement single-clock mode for FIFO,
ROM, true dual-port, simple dual-port, and single-port memories. In this mode, you
can control all registers of the M9K memory block with a single clock together with
clock enable.
This section describes designing with M9K memory blocks.
“Same-Port Read-During-Write Mode” on page 3–16
Write Mode” on page 3–17
configurations when reading from an address during a write operation at that same
address.
There are two read-during-write data flows: same-port and mixed-port.
shows the difference between these flows.
Figure 3–13. Cyclone IV Devices Read-During-Write Data Flow
write_a
read_a
Port A
data in
Port A
data out
describe the functionality of the various RAM
and
Port B
data in
Port B
data out
Cyclone IV Device Handbook, Volume 1
“Mixed-Port Read-During-
read_b
write_b
Figure 3–13
Mixed-port
data flow
Same-port
data flow
3–15
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