EP1S10F672C7 Altera, EP1S10F672C7 Datasheet - Page 115

• Manufacturer Part Number: EP1S10F672C7
• Description: IC STRATIX FPGA 10K LE 672-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F672C7

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 345
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 10570
• # I/os (max): 345
• Frequency (max): 420.17MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 10570
• Ram Bits: 920448
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1109

Figure 2–58. Stratix Device Fast PLL
Notes to
(1)
(2)
(3)
Altera Corporation
July 2005
Global or
regional clock (1)
Clock
Input
The global or regional clock input can be driven by an output from another PLL or any dedicated CLK or FCLK pin.
It cannot be driven by internally-generated global signals.
In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix devices only
support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a high-speed differential I/O support SERDES control signal.
Figure
2–58:
Frequency
Detector
Clock Multiplication & Division
Stratix device fast PLLs provide clock synthesis for PLL output ports
using m/(post scaler) scaling factors. The input clock is multiplied by the
m feedback factor. Each output port has a unique post scale counter to
divide down the high-frequency VCO. There is one multiply divider, m,
per fast PLL with a range of 1 to 32. There are two post scale L dividers
for regional and/or LVDS interface clocks, and g0 counter for global clock
output port; all range from 1 to 32.
In the case of a high-speed differential interface, set the output counter to
1 to allow the high-speed VCO frequency to drive the SERDES. When
used for clocking the SERDES, the m counter can range from 1 to 30. The
VCO frequency is equal to f
300 and 1000 MHz.
Phase
PFD
Charge
Pump
Loop
Filter
VCO Phase Selection
Selectable at each PLL
Output Port
÷m
IN
VCO
×m, where VCO frequency must be between
8
Stratix Device Handbook, Volume 1
Post-Scale
Counters
÷g0
÷l0
÷l1
Stratix Architecture
diffioclk1 (2)
Global or
regional clock
txload_en (3)
rxload_en (3)
Global or
regional clock
diffioclk2 (2)
Global or
regional clock
2–101