EP1S10F672C7 Altera, EP1S10F672C7 Datasheet - Page 195
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EP1S10F672C7
Manufacturer Part Number
EP1S10F672C7
Description
IC STRATIX FPGA 10K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F672C7
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
345
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
345
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1109
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F672C7
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S10F672C7
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Company:
Part Number:
EP1S10F672C7AA
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP1S10F672C7ES
Manufacturer:
ALTERA
Quantity:
89
Company:
Part Number:
EP1S10F672C7N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S10F672C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
January 2006
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M4KDATAAH
M4KADDRASU
M4KADDRAH
M4KDATABSU
M4KDATABH
M4KADDRBSU
M4KADDRBH
M4KDATACO1
M4KDATACO2
M4KCLKHL
M4KCLR
MRAMRC
MRAMWC
MRAMWERESU
MRAMWEREH
MRAMCLKENSU
MRAMCLKENH
MRAMBESU
MRAMBEH
MRAMDATAASU
MRAMDATAAH
MRAMADDRASU
MRAMADDRAH
MRAMDATABSU
Table 4–41. M4K Block Internal Timing Microparameter Descriptions (Part
2 of 2)
Table 4–42. M-RAM Block Internal Timing Microparameter
Descriptions (Part 1 of 2)
Symbol
Symbol
A port data hold time after clock
A port address setup time before clock
A port address hold time after clock
B port data setup time before clock
B port data hold time after clock
B port address setup time before clock
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Register minimum clock high or low time. This is a limit on
the min time for the clock on the registers in these blocks.
The actual performance is dependent upon the internal
point-to-point delays in the blocks and may give slower
performance as shown
reported by the timing analyzer in the Quartus II software.
Minimum clear pulse width
Synchronous read cycle time
Synchronous write cycle time
Write or read enable setup time before clock
Write or read enable hold time after clock
Clock enable setup time before clock
Clock enable hold time after clock
Byte enable setup time before clock
Byte enable hold time after clock
A port data setup time before clock
A port data hold time after clock
A port address setup time before clock
A port address hold time after clock
B port setup time before clock
Stratix Device Handbook, Volume 1
inTable 4–36 on page 4–20
Parameter
Parameter
DC & Switching Characteristics
and as
4–25