EP1S10F672C7 Altera, EP1S10F672C7 Datasheet - Page 205
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EP1S10F672C7
Manufacturer Part Number
EP1S10F672C7
Description
IC STRATIX FPGA 10K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F672C7
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
345
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
345
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1109
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F672C7
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S10F672C7
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Company:
Part Number:
EP1S10F672C7AA
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP1S10F672C7ES
Manufacturer:
ALTERA
Quantity:
89
Company:
Part Number:
EP1S10F672C7N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S10F672C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
January 2006
Table 4–54
clock networks.
Notes to
(1)
(2)
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
t
XZPLL
ZXPLL
INSU
INH
OUTCO
INSUPLL
INHPLL
OUTCOPLL
XZPLL
ZXPLL
Table 4–53. Stratix Regional Clock External I/O Timing Parameters (Part 2
of 2)
Table 4–54. Stratix Global Clock External I/O Timing Parameters
(2)
Symbol
Symbol
These timing parameters are sample-tested only.
These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
These timing parameters are sample-tested only.
These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
Notes
Table
Table
shows the external I/O timing parameters when using global
Setup time for input or bidirectional pin using IOE input register with
global clock fed by
Hold time for input or bidirectional pin using IOE input register with
global clock fed by
Clock-to-output delay output or bidirectional pin using IOE output
register with global clock fed by
Setup time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
Hold time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
Clock-to-output delay output or bidirectional pin using IOE output
register with global clock Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin disable delay
using global clock fed by Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin enable delay
using global clock fed by Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin disable delay
using regional clock fed by Enhanced PLL with default phase setting
Synchronous IOE output enable register to output pin enable delay
using regional clock fed by Enhanced PLL with default phase setting
(1),
4–53:
4–54:
(2)
CLK
CLK
pin
pin
Parameter
Parameter
Stratix Device Handbook, Volume 1
CLK
DC & Switching Characteristics
pin
Notes
(1),
4–35