EP1S10F672C7 Altera, EP1S10F672C7 Datasheet - Page 127
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EP1S10F672C7
Manufacturer Part Number
EP1S10F672C7
Description
IC STRATIX FPGA 10K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F672C7
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
345
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
345
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1109
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F672C7
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S10F672C7
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Company:
Part Number:
EP1S10F672C7AA
Manufacturer:
ALTERA
Quantity:
3 000
Company:
Part Number:
EP1S10F672C7ES
Manufacturer:
ALTERA
Quantity:
89
Company:
Part Number:
EP1S10F672C7N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S10F672C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–66. Input Timing Diagram in DDR Mode
Altera Corporation
July 2005
Input To
Logic Array
Data at
input pin
CLK
A'
B'
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from LEs on rising clock edges. These
output registers are multiplexed by the clock to drive the output pin at a
×2 rate. One output register clocks the first bit out on the clock high time,
while the other output register clocks the second bit out on the clock low
time.
shows the DDR output timing diagram.
A0
Figure 2–67
B1
A1
B2
shows the IOE configured for DDR output.
A1
B1
A2
B3
A2
B2
A3
B4
A3
B3
Stratix Device Handbook, Volume 1
Stratix Architecture
Figure 2–68
2–113