EP3C120F780C8N Altera, EP3C120F780C8N Datasheet - Page 102
![IC CYCLONE III FPGA 119K 780FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP3C120F780C8N
Manufacturer Part Number
EP3C120F780C8N
Description
IC CYCLONE III FPGA 119K 780FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C120F780C8N.pdf
(274 pages)
Specifications of EP3C120F780C8N
Number Of Logic Elements/cells
119088
Number Of Labs/clbs
7443
Total Ram Bits
3981312
Number Of I /o
531
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
119088
# I/os (max)
531
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
119088
Ram Bits
3981312
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2392
544-2533
544-2533
EP3C120F780C8NES
544-2533
544-2533
EP3C120F780C8NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C120F780C8N
Manufacturer:
ALTERA
Quantity:
642
Part Number:
EP3C120F780C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
6–2
Figure 6–1. Cyclone III Device Family IOE in a Bidirectional I/O Configuration
I/O Element Features
Programmable Current Strength
Cyclone III Device Handbook, Volume 1
Interconnect
Column
or Row
io_clk[5..0]
data_in1
data_in0
Figure 6–1
The Cyclone III device family IOE offers a range of programmable features for an I/O
pin. These features increase the flexibility of I/O utilization and provide an
alternative to reduce the usage of external discrete components to on-chip, such as a
pull-up resistor and a diode.
The output buffer for each Cyclone III device family I/O pin has a programmable
current strength control for certain I/O standards.
The LVTTL, LVCMOS, SSTL-2 Class I and II, SSTL-18 Class I and II, HSTL-18 Class I
and II, HSTL-15 Class I and II, and HSTL-12 Class I and II I/O standards have several
levels of current strength that you can control.
Chip-Wide Reset
shows the Cyclone III device family IOE structure.
OE
clkout
oe_out
aclr/prn
clkin
oe_in
preset
sclr/
Output Register
OE Register
ENA
ENA
D
D
ACLR
/PRN
ACLR
/PRN
Q
Q
Input Register
ENA
D
ACLR
/PRN
Current Strength Control
Q
Slew Rate Control
Open-Drain Out
Chapter 6: I/O Features in the Cyclone III Device Family
Pin Delay
Output
Input Register
or Input Pin to
Logic Array
Input Pin to
Delay
Delay
V
CCIO
© December 2009 Altera Corporation
V
CCIO
Programmable
I/O Element Features
Resistor
Pull-Up
Bus Hold