EP3C120F780C8N Altera, EP3C120F780C8N Datasheet - Page 92

• Manufacturer Part Number: EP3C120F780C8N
• Description: IC CYCLONE III FPGA 119K 780FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C120F780C8N

• Number Of Logic Elements/cells: 119088
• Number Of Labs/clbs: 7443
• Total Ram Bits: 3981312
• Number Of I /o: 531
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 119088
• # I/os (max): 531
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 119088
• Ram Bits: 3981312
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2392; 544-2533; 544-2533; EP3C120F780C8NES

5–28
Figure 5–23. Scan Chain Bit Order
Cyclone III Device Handbook, Volume 1
DATAOUT
HB
LB
0
0
HB
Table 5–4. Cyclone III Device Family PLL Reprogramming Bits (Part 2 of 2)
Figure 5–22
Figure 5–22. PLL Component Scan Chain Order
Figure 5–23
Cyclone III device family PLLs.
LB
1
1
N
Charge Pump
Loop Filter
Total number of bits:
Notes to
(1) LSB bit for C4 low-count value is the first bit shifted into the scan chain.
(2) These two control bits include rbypass, for bypassing the counter, and rselodd, to select the output clock
(3) MSB bit for loop filter is the last bit shifted into the scan chain.
Block Name
duty cycle.
DATAIN
HB
Table
LB
2
2
(3)
shows the scan chain order of the PLL components.
shows the scan chain bit order sequence for one PLL post-scale counter in
5–4:
HB
LB
3
3
DATAOUT
MSB
HB
LB
4
4
Counter
LF
16
9
9
HB
CP
LB
5
5
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
C4
LSB
HB
LB
6
6
Number of Bits
HB
LB
7
7
C3
N
Other
2
0
0
(2)
HB
LB
8
8
© December 2009 Altera Corporation
C2
M
LB
HB
9
9
PLL Reconfiguration
rselodd
Total
C0
C1
rbypass
144
18
9
9
DATAIN