EP3C120F780C8N Altera, EP3C120F780C8N Datasheet - Page 45

• Manufacturer Part Number: EP3C120F780C8N
• Description: IC CYCLONE III FPGA 119K 780FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C120F780C8N

• Number Of Logic Elements/cells: 119088
• Number Of Labs/clbs: 7443
• Total Ram Bits: 3981312
• Number Of I /o: 531
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 119088
• # I/os (max): 531
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 119088
• Ram Bits: 3981312
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2392; 544-2533; 544-2533; EP3C120F780C8NES

Chapter 3: Memory Blocks in the Cyclone III Device Family
Memory Modes
© December 2009
Altera Corporation
During a write operation, the behavior of the RAM outputs is configurable. If you
activate rden during a write operation, the RAM outputs show either the new data
being written or the old data at that address. If you perform a write operation with
rden deactivated, the RAM outputs retain the values they held during the most
recent active rden signal.
To choose the desired behavior, set the Read-During-Write option to either New Data
or Old Data in the RAM MegaWizard Plug-In Manager in the Quartus II software.
For more information about read-during-write mode, refer to
Operations” on page
The port width configurations for M9K blocks in single-port mode are as follow:
■
■
■
■
■
■
■
■
■
Figure 3–8
mode with unregistered outputs. Registering the outputs of the RAM simply delays
the q output by one clock cycle.
Figure 3–8. Cyclone III Device Family Single-Port Mode Timing Waveforms
8192 × 1
4096 × 2
2048 × 4
1024 × 8
1024 × 9
512 × 16
512 × 18
256 × 32
256 × 36
q_a (new data)
q_a (old data)
address_a
wren_a
rden_a
data_a
shows timing waveforms for read and write operations in single-port
clk_a
3–16.
A
a0(old data)
A
a0
B
B
A
C
C
B
D
a1(old data)
D
Cyclone III Device Handbook, Volume 1
a1
“Read-During-Write
E
E
D
F
F
E
3–9