EP1SGX25CF672C6 Altera, EP1SGX25CF672C6 Datasheet - Page 169

• Manufacturer Part Number: EP1SGX25CF672C6
• Description: IC STRATIX GX FPGA 25KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25CF672C6

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
February 2005
Programmable delays can increase the register-to-pin delays for output
and/or output enable registers. A programmable delay exists to increase
the t
Table 4–21
The IOE registers in Stratix GX devices share the same source for clear or
preset. You can program preset or clear for each individual IOE. You can
also program the registers to power up high or low after configuration is
complete. If programmed to power up low, an asynchronous clear can
control the registers. If programmed to power up high, an asynchronous
preset can control the registers. This feature prevents the inadvertent
activation of another device’s active-low input upon power-up. If one
register in an IOE uses a preset or clear signal then all registers in the IOE
must use that same signal if they require preset or clear. Additionally, a
synchronous reset signal is available for the IOE registers.
Double-Data Rate I/O Pins
Stratix GX devices have six registers in the IOE, which support DDR
interfacing by clocking data on both positive and negative clock edges.
The IOEs in Stratix GX devices support DDR inputs, DDR outputs, and
bidirectional DDR modes.
Input pin to logic array delay
Input pin to input register delay
Output pin delay
Output enable register t
Output t
Output clock enable delay
Input clock enable delay
Logic array to output register delay
Output enable clock enable delay
Table 4–21. Stratix GX Programmable Delay Chain
ZX
Programmable Delays
delay to the output pin, which is required for ZBT interfaces.
ZX
delay
shows the programmable delays for Stratix GX devices.
CO
delay
Decrease input delay to internal cells
Decrease input delay to input register
Increase delay to output pin
Increase delay to output enable pin
Increase t
Increase output clock enable delay
Increase input clock enable delay
Decrease input delay to output register
Increase output enable clock enable delay
Stratix GX Device Handbook, Volume 1
Quartus II Logic Option
ZX
delay to output pin
Stratix GX Architecture
4–103