EP1SGX25CF672C6 Altera, EP1SGX25CF672C6 Datasheet - Page 231

• Manufacturer Part Number: EP1SGX25CF672C6
• Description: IC STRATIX GX FPGA 25KLE 672FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25CF672C6

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
June 2006
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MRAMDATABSU
MRAMDATABH
MRAMADDRBSU
MRAMADDRBH
MRAMDATACO1
MRAMDATACO2
MRAMCLKHL
MRAMCLR
R4
R8
R24
C4
C8
C16
LOCAL
A N A L O G R E S E T P W
D I G I T A L R E S E T P W
T X _ P L L _ L O C K
Table 6–41. M-RAM Block Internal Timing Microparameter
Descriptions (Part 2 of 2)
Table 6–42. Routing Delay Internal Timing Microparameter Descriptions
Table 6–43. Stratix GX Reset & PLL Lock Time Parameter Descriptions
(Part 1 of 2)
Symbol
Symbol
Symbol
B port setup time before clock
B port hold time after clock
B port address setup time before clock
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Minimum clock high or low time
Minimum clear pulse width
Delay for an R4 line with average loading; covers a distance
of four LAB columns
Delay for an R8 line with average loading; covers a distance
of eight LAB columns
Delay for an R24 line with average loading; covers a distance
of 24 LAB columns
Delay for an C4 line with average loading; covers a distance
of four LAB rows
Delay for an C8 line with average loading; covers a distance
of eight LAB rows
Delay for an C16 line with average loading; covers a distance
of 16 LAB rows
Local interconnect delay
Pulse width to power down analog circuits.
Pulse width to reset digital circuits
The time it takes the
reference clock.
Stratix GX Device Handbook, Volume 1
Parameter
Parameter
DC & Switching Characteristics
Parameter
tx_pll
to lock to the
6–29