EP4SE530H40C3 Altera, EP4SE530H40C3 Datasheet - Page 264
EP4SE530H40C3
Manufacturer Part Number
EP4SE530H40C3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Quantity:
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- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Figure 7–24. Stratix IV DQS Logic Block
Notes to
(1) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For more information, refer to
(2) The dqsenable signal can also come from the Stratix IV FPGA fabric.
Figure
DQS Logic Block
DQS delay
settings from the
DQS phase-shift
circuitry
Phase offset
settings from the
DQS phase-shift
circuitry
7–24:
offsetctrlin [5:0]
Each DQS/CQ and CQn pin is connected to a separate DQS logic block, which consists of the DQS delay chains, update enable
circuitry, and DQS postamble circuitry, as shown in
delayctrlin [5:0]
6
6
DQS/CQ or
CQn Pin
<dqs_offsetctrl_enable>
1
0
6
D
Bypass
Q
Input Reference
Clock (1)
6
1
0
dqsin
DQS Delay Chain
6
D
Q
dqsupdateen
6
1
0
<dqs_ctrl_latches_enable>
6
Update
Enable
Circuitry
Figure
Resynchronization
phasectrlin[2:0]
Postamble
Enable
Clock
7–24.
1xx
000
001
010
011
dqsenablein
DQS Enable Control
dqsbusout
clk
dqsin
DQS Enable
enaphasetransferreg
<level_dqs_enable>
0
1
delayctrlin
Table 7–5 on page 7–33
0
1
dqsbusout
6
DQS bus
<delay_dqs_enable_by_half_cycle>
postamble control clock
phasectrlin
0110
0101
0100
0011
0010
0001
0000
0111
Q
4
PRE
dqsenable (2)
through
D
phaseinvertctrl
0
1
dqsenableout
Table 7–17 on page
0
1
7–40.
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