EP4SE530H40C3 Altera, EP4SE530H40C3 Datasheet - Page 904
EP4SE530H40C3
Manufacturer Part Number
EP4SE530H40C3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SE230F29C3N PDF datasheet #6
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5–58
Figure 5–29. Correct Input Reference Clock Connections When Reusing a .mif
Note to
(1) The red lines represent the alternate source of REFCLK.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
5–29:
1
156.25 MHz
125 MHz
Figure 5–29
You can re-use the .mif generated for a transceiver channel on one side of the device
for a transceiver channel on the other side of the device, only if the input reference
clock frequencies and order of the pll_inclk_rx_cruclk[] ports in the ALTGX
instances on both sides are identical.
In addition to the input reference clock requirements when re-using a .mif, refer to
“Guidelines for logical_tx_pll_sel and logical_tx_pll_sel_en Ports” on page 5–58
additional ways to re-use a .mif.
Guidelines for logical_tx_pll_sel and logical_tx_pll_sel_en Ports
This section describes when to enable the logical_tx_pll_sel and
logical_tx_pll_sel_en ports and how to use them in the following dynamic
reconfiguration modes:
■
■
■
These are optional input ports to the ALTGX_RECONFIG instance.
Channel and CMU PLL reconfiguration mode
Channel reconfiguration with transmitter PLL select mode
CMU PLL reconfiguration mode
shows the correct input reference clock connections when re-using a .mif.
(1)
(1)
pll_inclk_rx_cruclk[0]
pll_inclk_rx_cruclk[1]
pll_inclk_rx_cruclk[0]
pll_inclk_rx_cruclk[1]
Stratix IV GX Device
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Transceiver Block 0
Transceiver Block 1
Instance 2
Instance 1
ALTGX
February 2011 Altera Corporation
ALTGX
for
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