EP4SE530H40C3 Altera, EP4SE530H40C3 Datasheet - Page 513
EP4SE530H40C3
Manufacturer Part Number
EP4SE530H40C3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–31. Word Aligner Options Available in Basic Single-Width and Double-Width Modes
February 2011 Altera Corporation
Basic
Single-Width
Functional
Mode
PMA-PCS
Interface
Width
10-bit
8-bit
Table 1–31
double-width modes.
Word Alignment
Synchronization
State Machine
Alignment
Alignment
Automatic
Manual
Bit-Slip
Manual
Bit-Slip
Mode
lists the word aligner options available in Basic single-width and
7- and 10-bit
7- and 10-bit
7- and 10-bit
Alignment
Pattern
Length
16-bit
16-bit
Word
rx_enapatternalign
Level Sensitive
Rising Edge
Sensitivity
Sensitive
N/A
N/A
N/A
Stratix IV Device Handbook Volume 2: Transceivers
Asserted high for
one parallel clock
cycle when the
word aligner
aligns to a new
word boundary.
Asserted high for
one parallel clock
cycle when the
word aligner
aligns to a new
word boundary.
Stays high as
long as the
synchronization
conditions are
satisfied.
rx_syncstatus
Behavior
N/A
N/A
(Note 1)
(Part 1 of 2)
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
Asserted high for
one parallel clock
cycle when the
word alignment
pattern appears in
the current word
boundary.
rx_patterndetect
Behavior
1–69
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