EP4SE530H40C3 Altera, EP4SE530H40C3 Datasheet - Page 700
EP4SE530H40C3
Manufacturer Part Number
EP4SE530H40C3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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2–28
Figure 2–16. Transmitter Datapath Clocking in x4 Bonded Configurations
Note to
(1) The red lines represent the FPGA fabric-Transceiver interface clock, the green lines represent the low-speed parallel clock, and the blue lines
Stratix IV Device Handbook Volume 2: Transceivers
represent the high-speed serial clock.
tx_coreclk[2]
tx_coreclk[3]
tx_coreclk[0]
tx_coreclk[1]
FPGA
Fabric
Figure
2–16:
coreclkout
hard IP
hard IP
hard IP
hard IP
FPGA Fabric-Transceiver
PCIe
FPGA Fabric-Transceiver
PCIe
PCIe
PCIe
FPGA Fabric-Transceiver
FPGA Fabric-Transceiver
Interface Clock
Interface Clock
Interface Clock
Interface Clock
Figure 2–16
configurations when clocked using the CMU0 channel.
Interface
Interface
Interface
Interface
/
2
PIPE
PIPE
PIPE
PIPE
Reference
Reference
Clock
Clock
Input
Input
shows the transmitter channel datapath clocking in ×4 channel bonding
CMU1 PLL
CMU0 PLL
Compensation
wrclk
Compensation
Compensation
wrclk
wrclk
wrclk
Compensation
TX Phase
TX Phase
TX Phase
TX Phase
FIFO
FIFO
FIFO
FIFO
rdclk
rdclk
rdclk
rdclk
wrclk
wrclk
wrclk
wrclk
Serializer
Serializer
Serializer
Serializer
Divider
CMU0
Clock
Byte
Byte
Byte
Byte
/
/
/2
/
2
2
2
rdclk
rdclk
rdclk
rdclk
CMU0 Channel x4 Low-Speed Parallel Clock
CMU1 Channel
x4 Low-Speed Parallel Clock
Transmitter Channel PCS
x4 Low-SPeed Parallel Clock
Transmitter Channel PCS
x4 Low-Speed Parallel Clock
x4 Low-Speed Parallel Clock
Transmitter Channel PCS
Transmitter Channel PCS
Chapter 2: Transceiver Clocking in Stratix IV Devices
(Note 1)
8B/10B
Encoder
8B/10B
Encoder
x4 High-Speed Serial Clock
8B/10B
Encoder
8B/10B
Encoder
Channel 1
Channel 0
Channel 3
Channel 2
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Serializer
Serializer
Serializer
Serializer
x4 High-Speed Serial Clock
x4 High-Speed Serial Clock
x4 High-Speed Serial Clock
x4 High-Speed Serial Clock
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