EP4SE530H40C3 Altera, EP4SE530H40C3 Datasheet - Page 903
EP4SE530H40C3
Manufacturer Part Number
EP4SE530H40C3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–28. Incorrect Input Reference Clock Connections When Reusing a .mif
Note to
(1) The red lines represent the alternate source of REFCLK.
February 2011 Altera Corporation
Figure
5–28:
f
156.25 MHz
125 MHz
For more information about input reference clocking, refer to the “Input Reference
Clocking” section of the
The following section describes the clocking requirements to re-use .mifs.
The .mif contains information about the input clock multiplexer settings and the
functional blocks that you selected during the ALTGX MegaWizard Plug-In Manager
instantiation. You can use a .mif to dynamically reconfigure any of the other
transceiver channels in the device as long as the order of the clock inputs is consistent.
For example, assume that a .mif is generated for a transceiver channel in transceiver
block 0 and the input clock source is connected to the pll_inclk_rx_cruclk[0] port.
When you use the generated .mif for a channel in other transceiver blocks (for
example, transceiver block 1), the same clock source must be connected to the
pll_inclk_rx_cruclk[0] port.
correct order of input reference clocks, respectively.
In
reference clock is not connected to the corresponding pll_inclk_rx_cruclk[] ports in
the two instances.
Figure
5–28, the clocking is incorrect when re-using the .mif because the input
(1)
Transceiver Clocking in Stratix IV Devices
(1)
Figure 5–28
pll_inclk_rx_cruclk[0]
pll_inclk_rx_cruclk[1]
pll_inclk_rx_cruclk[0]
pll_inclk_rx_cruclk[1]
Stratix IV GX Device
and
Figure 5–29
Stratix IV Device Handbook Volume 2: Transceivers
Transceiver Block 0
Transceiver Block 1
show the incorrect and
Instance 1
Instance 2
ALTGX
ALTGX
chapter.
5–57
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