EP4SE530H40C3 Altera, EP4SE530H40C3 Datasheet - Page 459
EP4SE530H40C3
Manufacturer Part Number
EP4SE530H40C3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Channel Locations
February 2011 Altera Corporation
Figure 1–10
the EP4S100G5F45 Stratix IV GT devices.
Figure 1–10. Transceiver Channel, PLL, and PCIe Hard IP Block Locations in EP4S100G5F45
Stratix IV GT Devices
Note to
(1) EP4S100G5F45 devices are the same as EP4S100G3F45 and EP4S100G4F45 devices except that the GXBR0
transceiver block is 10G instead of 8G.
Figure
1–10:
shows the transceiver channel, PLL, and PCIe hard IP block locations for
Transceiver Block QL0
Transceiver Block QL0
Transceiver Block QL2
Channel 3 (10G)
Channel 2 (10G)
Channel 1 (10G)
Channel 0 (10G)
CMU Channel 1
CMU Channel 0
EP4S100G5F45
Transceiver Block QL1
Channel 3 (10G)
Channel 2 (10G)
Channel 1 (10G)
Channel 0 (10G)
Channel 3 (10G)
Channel 2 (10G)
Channel 1 (10G)
Channel 0 (10G)
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
Channel 3 (10G)
Channel 2 (10G)
Channel 1 (10G)
Channel 0 (10G)
CMU Channel 1
CMU Channel 0
ATX PLL (10G)
ATX PLL (6G)
ATX PLL (6G)
(Note 1)
Stratix IV Device Handbook Volume 2: Transceivers
Transceiver Block QR0
Transceiver Block QR2
Transceiver Block QR1
Transceiver Block QR0
Channel 3 (10G)
Channel 2 (10G)
Channel 1 (10G)
Channel 0 (10G)
Channel 3 (10G)
Channel 2 (10G)
Channel 1 (10G)
Channel 0 (10G)
Channel 3 (10G)
Channel 2 (10G)
Channel 1 (10G)
Channel 0 (10G)
ATX PLL (10G)
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
Channel 3 (10G)
Channel 2 (10G)
Channel 1 (10G)
Channel 0 (10G)
CMU Channel 1
CMU Channel 0
ATX PLL (6G)
CMU Channel 1
CMU Channel 0
ATX PLL (6G)
1–15
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