EP4SE530H40C3 Altera, EP4SE530H40C3 Datasheet - Page 635
EP4SE530H40C3
Manufacturer Part Number
EP4SE530H40C3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #3
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–155. Serial Loopback Datapath
February 2011 Altera Corporation
FPGA
Fabric
Compen-
1
Phase
Compen-
sation
FIFO
Phase
sation
TX
FIFO
RX
When moving into or out of serial loopback, you must assert rx_digitalreset for a
minimum of two parallel clock cycles.
Parallel Loopback
You can configure a transceiver channel in this mode by setting the which protocol
will you be using? field to Basic and the which sub protocol will you be using? field
to BIST. You can only configure a Receiver and Transmitter transceiver channel in
this functional mode. You can configure a transceiver channel in this mode in either a
single-width or double-width configuration.
The BIST pattern generator and pattern verifier are located near the FPGA fabric in
the PCS block of the transceiver channel. This placement allows for testing the
complete transmitter PCS and receiver PCS datapaths for bit errors. This mode is
primarily used for transceiver channel debugging, if needed.
Ordering
Byte
Serializer
Byte
serializer
Byte
De-
Encoder
8B/10B
BIST PRBS, High-Freq,
Low-Freg pattern
Receiver Channel PCS
Decoder
8B/10B
generator
Match
FIFO
Rate
Transmitter Channel PCS
BIST PRBS verifier
Deskew
FIFO
Stratix IV Device Handbook Volume 2: Transceivers
Aligner
Word
serializer
Receiver Channel
Serializer
Transmitter Channel PMA
De-
PMA
Receiver
CDR
can be dynamically enabled
Serial loop back
1–191
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