EP4SE530H40C3 Altera, EP4SE530H40C3 Datasheet - Page 604
EP4SE530H40C3
Manufacturer Part Number
EP4SE530H40C3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SE230F29C3N PDF datasheet #6
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1–160
Figure 1–126. IEEE 802.3ae PCS Synchronization State Diagram
Note to
(1) This figure is from IEEE P802.3ae.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
1–126:
Word Aligner
The word aligner in XAUI functional mode is configured in automatic
synchronization state machine mode. The Quartus II software automatically
configures the synchronization state machine to indicate synchronization when the
receiver receives four /K28.5/ comma code groups without intermediate invalid code
groups. The synchronization state machine implemented in XAUI mode is compliant
to the PCS synchronization state diagram specified in Clause 48 of the IEEE P802.3ae
specification and is shown in
2
3
rx_even
SUDI
good_cgs
rx_even
SUDI
good_cgs
rx_even
SUDI
good_cgs
SYNC_ACQUIRED_2
SYNC_ACQUIRED_3
SYNC_ACQUIRED_4
cgbad
cgbad
cgbad
[PUDI * signal_detect=FAIL +
mr_loopback=FALSE] +
PUDI(![/COMMA/])
⇐
⇐
⇐
⇐
⇐
⇐
! rx_even
! rx_even
! rx_even
0
0
0
PUDI(![/|DV|/]
cgbad
PUDI(![/|DV|/]
cgbad
PUDI(![/|DV|/]
cggood
cggood
cggood
Figure
SUDI
SUDI
SUDI
SUDI
SUDI
SUDI
rx_even
rx_even
COMMA_DETECT_1
rx_even
COMMA_DETECT_2
COMMA_DETECT_3
sync_status
ACQUIRE_SYNC_1
ACQUIRE_SYNC_2
LOSS_OF_SYNC
rx_even
rx_even
rx_even
cgbad
cgbad
cgbad
cgbad
⇐
⇐
⇐
⇐
⇐
⇐
! rx_even
! rx_even
! rx_even
PUDI([/|DV|/]
rx_even=FALSE+PUDI([/COMMA/]
PUDI([/|DV|/]
rx_even=FALSE+PUDI([/COMMA/]
(signal_detect=OK+mr_loopback=TRUE)* *
PUDI([/COMMA/]
1–126.
TRUE
TRUE
TRUE
⇐
rx_even
SUDI
good_cgs
rx_even
SUDI
good_cgs
rx_even
SUDI
good_cgs
SYNC_ACQUIRED_2A
SYNC_ACQUIRED_3A
SYNC_ACQUIRED_4A
(Note 1)
FAIL
PUDI([/|DV|/]
power_on=TRUE+mr_main_rest=TRUE +
(signal_detectCHANGE=TRUE +
mr_loopback=FALSE +PUDI)
⇐
⇐
⇐
⇐
⇐
⇐
! rx_even
! rx_even
! rx_even
2
3
good_cgs + 1
good_cgs + 1
good_cgs + 1
Chapter 1: Transceiver Architecture in Stratix IV Devices
cggood
cggood
PUDI(![/COMMA/]
*∉[/INVALID/]
PUDI(![/COMMA/]
*∉[/INVALID/]
SUDI
SYNC_ACQUIRED_1
*good_cgs = 3
*good_cgs = 3
rx_even
sync_status
⇐
cggood
cggood
cggood
! rx_even
⇐
cggood
OK
*good_cgs = 3
*good_cgs = 3
*good_cgs = 3
*good_cgs = 3
cggood
February 2011 Altera Corporation
Transceiver Block Architecture
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