EP4SE530H40C3 Altera, EP4SE530H40C3 Datasheet - Page 786
EP4SE530H40C3
Manufacturer Part Number
EP4SE530H40C3
Description
IC STRATIX IV FPGA 530K 1517HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H40C3
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
976
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-HBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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- EP4SGX110DF29C3N PDF datasheet
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- EP4SE230F29C3N PDF datasheet #6
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3–32
Stratix IV Device Handbook Volume 2: Transceivers
1
Figure 3–17
after compilation.
Figure 3–17. Combining Basic (PMA Direct) ×1 and Non-Basic (PMA Direct) Instances in a
Transceiver Block After Compilation for Example 7
Key Observations
To combine the these instances, two CMU PLLs are required due to the different data
rates. Therefore, two CMU channels must be available to enable their respective CMU
PLLs. Note that inst3 uses the transmit side of the CMU channel that uses the CMU
PLL for clock generation.
shows Basic (PMA Direct) ×1 and non-Basic (PMA Direct) configurations
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
inst3: TX
RX
Inst0: Channel (GIGE)
RX
Inst1: Channel 1
Inst1: Channel 2
RX
RX
Inst1: Channel 0
(1.25 Gbps)
CMU PLL
Combining Transceiver Channels in Basic (PMA Direct) Configurations
GXBR
CMU PLL
(2 Gbps)
TX
TX
TX
TX
February 2011 Altera Corporation
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