XC4VFX60-10FFG1152I Xilinx Inc, XC4VFX60-10FFG1152I Datasheet - Page 108

• Manufacturer Part Number: XC4VFX60-10FFG1152I
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Phase-Matched Clock Dividers (PMCDs)
108
PMCD for Further Division of Clock Frequencies
PMCDs can be used to further divide clock frequencies. A dedicated local connection
exists from the CLKA1D8 output of each PMCD to the CLKA input of the other PMCD
within the same tile (group of two). Thus, only CLKA1D8 can directly connect two PMCDs
in series.
Figure 3-11
Note the following guidelines:
•
•
Reset
Logic to synchronize REL from
the PMCD output clock domain
to the PMCD input clock domain.
GCLK
The CLKDV output is connected to CLKA of PMCD to allow further frequency
division.
The CLK0 feedback clock is connected to CLKB, and the RST_DEASSERT_CLK
attribute is set to CLKB. These connections and settings ensure synchronous PMCD
outputs.
IOB
CLKDV_DIVIDE = 16
CLKIN
CLKFB
RST
illustrates an example of dividing clock frequencies using a DCM and a PMCD.
Figure 3-10: PMCD Driven by BUFG and Synchronous Logic
Figure 3-11: DCM to PMCD for Clock Frequency Division
DCM
BUFG
LOCKED
CLKDV
CLK0
www.xilinx.com
Synchronous
f/16
Logic
CLBs
Reset
RST_DEASSERT_CLK = CLKB
EN_REL = FALSE
Reset
CLKB
CLKA
RST
REL
RST_DEASSERT_CLK = CLKA
EN_REL = TRUE
CLKA
RST
REL
PMCD
CLKA1D8
PMCD
UG070 (v2.6) December 1, 2008
CLKB1
CLKA1D2
CLKA1D4
CLKA1D8
Virtex-4 FPGA User Guide
CLKA1
BUFGs
UG070_3_10_071404
UG070_3_11_071404
BUFGs
f/128
R