XC4VFX60-10FFG1152I Xilinx Inc, XC4VFX60-10FFG1152I Datasheet - Page 234

• Manufacturer Part Number: XC4VFX60-10FFG1152I
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 6: SelectIO Resources
SelectIO Resources Introduction
SelectIO Technology Resources General Guidelines
234
All Virtex-4 FPGAs have configurable high-performance SelectIO™ technology drivers
and receivers, supporting a wide variety of standard interfaces. The robust feature set
includes programmable control of output strength and slew rate, and on-chip termination
using Digitally Controlled Impedance (DCI). All banks can support 3.3V I/O.
Each IOB contains both input, output, and 3-state SelectIO drivers. These drivers can be
configured to various I/O standards. Differential I/O uses the two IOBs grouped together
in one tile.
•
•
Note:
Each Virtex-4 FPGA I/O tile contains two IOBs, and also two ILOGIC blocks and two
OLOGIC blocks, as described in
Figure 6-2
Each IOB has a direct connection to an ILOGIC/OLOGIC pair containing the input and
output logic resources for data and 3-state control for the IOB. When using multiple clocks
in Virtex-4 FPGA I/O tiles, the input clocks to the two ILOGIC blocks and the two
OLOGIC blocks are not shared. Both ILOGIC and OLOGIC can be configured as ISERDES
and OSERDES, respectively, as described in
Resources.”
This section summarizes the general guidelines to be considered when designing with the
SelectIO technology resources of Virtex-4 FPGAs.
DIFFI_IN
Single-ended I/O standards (LVCMOS, LVTTL, HSTL, SSTL, GTL, PCI)
Differential I/O standards (LVDS, LDT, LVPECL, BLVDS, CSE Differential HSTL and
SSTL)
Differential and V
O
T
shows the basic IOB and its connections to the internal logic and the device pad.
REF
www.xilinx.com
-dependent inputs are powered by V
Figure 6-2: Basic IOB Diagram
Chapter 7, “SelectIO Logic
OUTBUF
PAD
Chapter 8, “Advanced SelectIO Logic
INBUF
CCAUX
Resources”.
UG070 (v2.6) December 1, 2008
.
Virtex-4 FPGA User Guide
DIFFO_IN
ug070_6_02_071904
PADOUT
DIFFO_OUT
I
R