XC4VFX60-10FFG1152I Xilinx Inc, XC4VFX60-10FFG1152I Datasheet - Page 216

• Manufacturer Part Number: XC4VFX60-10FFG1152I
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Configurable Logic Blocks (CLBs)
CLB Primitives and Verilog/VHDL Examples
216
Distributed RAM Primitives
•
Four primitives are available; from 16 x 1-bit to 64 x 1-bit. Three primitives are single-port
RAM, and one primitive is a dual-port RAM, as shown in
Table 5-9: Single-Port and Dual-Port Distributed RAM
The input and output data are 1-bit wide. However, several distributed RAMs can be used
to implement wide memory blocks.
Figure 5-28
and DPRA signals are address busses.
As shown in
Table 5-10: Wider Primitives
RAM16X1S
RAM32X1S
RAM64X1S
RAM16X1D
RAM16X2S
RAM32X2S
RAM16X4S
Primitive
At time T
this case) becomes valid-High, resetting the slice register. This is reflected on either the
XQ or YQ pin at time T
Primitive
WCLK
Figure 5-28: Single-Port and Dual-Port Distributed RAM Primitive
A[#:0]
shows generic single-port and dual-port distributed RAM primitives. The A
WE
Table
D
SRCK
16 x 2-bit
32 x 2-bit
16 x 4-bit
RAM Size
before clock event 3, the SR signal (configured as synchronous reset in
5-10, wider primitives are available for 2-bit, 4-bit, and 8-bit RAM.
RAM#X1S
16 bits
32 bits
64 bits
16 bits
www.xilinx.com
RAM Size
CKO
D1, D0
D1, D0
D3, D2, D1, D0
Data Inputs
after clock event 3.
O
single-port
single-port
single-port
dual-port
Type
A3, A2, A1, A0
A3, A2, A1, A0
DPRA[#:0]
A4, A3, A2, A1, A0
WCLK
A[#:0]
Address Inputs
WE
D
Table
A3, A2, A1, A0
A4, A3, A2, A1, A0
A5, A4, A3, A2, A1, A0
A3, A2, A1, A0
RAM16X1D
UG070 (v2.6) December 1, 2008
Read Port
R/W Port
5-9.
Virtex-4 FPGA User Guide
Address Inputs
ug070_5_28_071504
O1, O0
O1, O0
O3, O2, O1, O0
Data Outputs
SPO
DPO
R