XC4VFX60-10FFG1152I Xilinx Inc, XC4VFX60-10FFG1152I Datasheet - Page 306

• Manufacturer Part Number: XC4VFX60-10FFG1152I
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 6: SelectIO Resources
Simultaneous Switching Output Limits
306
Sparse-Chevron Packages
Mixing Techniques
Summary
Regulating V
The following section discusses alternatives for managing overshoot and undershoot for
LVTTL, LVCMOS33, and PCI applications.
When V
limits any overshoot higher than 3.5V before reaching the absolute maximum level of
4.05V. In addition, instead of –0.3V when V
corresponding to V
undershoot before reaching the lower absolute maximum limit.
As a result, lowering V
for all supported 3.3 V standards, including LVCMOS_33, LVTTL, LVDCI_33, and PCI.
Either using LVDCI_33 standard or lowering the V
address overshoot and undershoot. It is also acceptable to combine both methods. When
V
The VRP and VRN values should always be the same as the board trace impedance.
Virtex-4 devices support 3.3V I/O standards (LVTTL, LVCMOS33, LVDCI33, PCI33/66,
and PCI-X) when the following guidelines are met:
•
•
When multiple output drivers change state at the same time, power supply disturbance
occurs. These disturbances can cause undesired transient behavior in output drivers, input
receivers, or in internal logic. These disturbances are often referred to as Simultaneous-
Switching Output (SSO) noise. The SSO limits govern the number and type of I/O output
drivers that can be switched simultaneously while maintaining a safe level of SSO noise.
The Virtex-4 FPGA SSO limits are divided into two categories: Sparce Chevron (SC) and
Non-Sparse Chevron (NSC), corresponding to package pinout style. SSO limits for SC
packages are simpler and less restrictive than for NSC packages.
Virtex-4 FPGA packaging falls into two categories according to pinout: sparse-chevron and
non-sparse-chevron. The sparse-chevron pinout style is an improvement over previous
designs, offering lower crosstalk and SSO noise. The pinout is designed to minimize PDS
inductance and keep I/O signal return current paths very closely coupled to their
associated I/O signal.
CCO
Keep signal overshoot and undershoot within the absolute maximum FPGA device
specifications.
♦
♦
♦
♦
The absolute maximum junction temperature (T
is lowered to 3.0V, it is not necessary to adjust the reference resistors VRP and VRN.
CCO
Source termination using LVDCI_33
Slow slew rate and/or reduced drive current
Voltage regulation at 3.0V
External high-speed bus switches
is lowered to 3.0V, the power clamp diode turns on at about 3.5V. Therefore it
CCO
CCO
at 3.0V
CCO
= 3.0V is –1.05V. In this case, the ground clamp diode clips
www.xilinx.com
to 3.0V addresses the overshoot and undershoot specifications
CCO
= 3.75V, the lower absolute maximum limit
CCO
J
) is 125°C for 3.3V I/O operation.
to 3.0V is a good approach to
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R