XC4VFX60-10FFG1152I Xilinx Inc, XC4VFX60-10FFG1152I Datasheet - Page 354

• Manufacturer Part Number: XC4VFX60-10FFG1152I
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 7: SelectIO Logic Resources
354
Output DDR Overview (ODDR)
Combinatorial Output Data and 3-State Control Path
OPPOSITE_EDGE Mode
The combinatorial output paths create a direct connection from the FPGA fabric to the
output driver or output driver control. These paths is used when:
1.
2.
Virtex-4 devices have dedicated registers in the OLOGIC to implement output DDR
registers. This feature is accessed when instantiating the ODDR primitive. DDR
multiplexing is automatic when using OLOGIC. No manual control of the mux-select is
needed. This control is generated from the clock.
There is only one clock input to the ODDR primitive. Falling edge data is clocked by a
locally inverted version of the input clock. All clocks feeding into the I/O tile are fully
multiplexed, i.e., there is no clock sharing between ILOGIC or OLOGIC blocks. The ODDR
primitive supports the following modes of operation:
•
•
The SAME_EDGE mode is new for the Virtex-4 architecture. This new mode allows
designers to present both data inputs to the ODDR primitive on the rising-edge of the
ODDR clock, saving CLB and clock resources, and increasing performance. This mode is
implemented using the DDR_CLK_EDGE attribute. It is supported for 3-state control as
well. The following sections describe each of the modes in detail.
In OPPOSITE_EDGE mode, two output registers are used to clock data from the FPGA
fabric at twice the throughput of a single rising-edge clocking scheme.
Both registers are rising-edge triggered. A second register receives an inverted version of
the clock. Both register outputs are then multiplexed and presented to the data input or
3-state control input of the IOB. This structure is similar to the Virtex-II and Virtex-II Pro
FPGA implementation. The simplified output DDR registers and the signals associated
with the OPPOSITE_EDGE mode are shown in
There is direct (unregistered) connection from logic resources in the FPGA fabric to the
output data or 3-state control.
The “pack I/O register/latches into IOBs” is set to OFF.
OPPOSITE_EDGE mode
SAME_EDGE mode
www.xilinx.com
Figure
7-21.
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
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