XC4VFX60-10FFG1152I Xilinx Inc, XC4VFX60-10FFG1152I Datasheet - Page 76

• Manufacturer Part Number: XC4VFX60-10FFG1152I
• Description: IC FPGA VIRTEX-4 FX 60K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX60-10FFG1152I

• Number Of Logic Elements/cells: 56880
• Number Of Labs/clbs: 6320
• Total Ram Bits: 4276224
• Number Of I /o: 576
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-BBGA, FCBGA
• For Use With: HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Digital Clock Managers (DCMs)
76
Phase Shifting
Frequency Synthesizer Characteristics
Phase-Shifting Operation
Virtex-4 Data
M ÷ D and generates the correct output frequencies.
For example, assume an input frequency of 50 MHz, M = 25, and D = 8 (M and D values do
not have common factors and cannot be reduced). The output frequency is 156.25 MHz
although separate calculations, 25 x 50 MHz = 1.25 GHz and 50 MHz ÷ 8 = 6.25 MHz,
seem to produce separate values outside the range of the input frequency.
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The DCM provides coarse and fine-grained phase shifting. For coarse-phase control, the
CLK0, CLK90, CLK180, and CLK270 outputs are each phase-shifted by ¼ of the input clock
period relative to each other. Similarly, CLK2X180 and CLKFX180 provide a 180° coarse
phase shift of CLK2X and CLKFX, respectively. The coarse phase-shifted clocks are
produced from the delay lines of the DLL circuit. The phase relationship of these clocks is
retained when CLKFB is not connected.
Fine-grained phase shifting uses the CLKOUT_PHASE_SHIFT and PHASE_SHIFT
attributes to phase-shift DCM output clocks relative to CLKIN. Since the CLKIN is used as
the reference clock, the feedback (CLKFB) connection is required for the phase-shifting
circuit to compare the incoming clock with the phase-shifted clock. The rest of this section
describes fine-grained phase shifting in the Virtex-4 FPGA DCM.
All nine DCM output clocks are adjusted when fine-grained phase shifting is activated.
The phase shift between the rising edges of CLKIN and CLKFB is a specified fraction of the
input clock period or a specific amount of DCM_TAP. All other DCM output clocks retain
their phase relation to CLK0.
The frequency synthesizer provides an output frequency equal to the input frequency
multiplied by M and divided by D.
The outputs CLKFX and CLKFX180 always have a 50/50 duty-cycle.
Smaller M and D values achieve faster lock times. Whenever possible, divide M and D
by the largest common factor to get the smallest values. (e.g., if the required
CLKFX = 9/6 x CLKIN, instead of using M = 9 and D = 6, use M = 3 and D = 2.)
When CLKFB is connected, CLKFX is phase aligned with CLK0 every D cycles of
CLK0 and every M cycles of CLKFX if M/D is a reduced fraction.
In the case where only the DFS outputs are used (CLKFB is not connected) and the
CLKIN of the DCM is outside the range of the DLL outputs, the
DCM_AUTOCALIBRATION attribute must be set to FALSE and the CONFIG
STEPPING constraint set to the proper production stepping level.
In the case where only DFS outputs are used, and when CLKIN of the DCM is outside
of the range for DLL outputs, a macro must be used to properly monitor the LOCKED
signal. Verilog and VHDL versions of the macro can be downloaded from
https://secure.xilinx.com/webreg/clickthrough.do?cid=30163.
Note:
and later XC4VFX devices.
This macro is not required for Step 1 and later XC4VLX and XC4VSX devices and SCD1
Sheet, it multiplies the incoming frequencies by the pre-calculated quotient
www.xilinx.com
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
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