XC2018-70PC84C Xilinx Inc, XC2018-70PC84C Datasheet - Page 19

• Manufacturer Part Number: XC2018-70PC84C
• Description: IC LOGIC CL ARRAY 1800GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC2000r

Specifications of XC2018-70PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 17878
• Number Of I /o: 74
• Number Of Gates: 1500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 93+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1004

Master Parallel Mode Programming Switching Characteristics
Note: 1. CCLK and DOUT timing are the same as for slave mode.
This timing diagram shows that the EPROM requirements are extremely relaxed: EPROM access time can be longer than
4000 ns, EPROM data output has no hold time requirement
RCLK
(output)
(output)
(output)
(output)
A0-A15
2. At power-up, V
D0-D7
DOUT
RCLK
CCLK
layed by holding RESET Low until V
a non-monotonically rising V
D/P after V
CC
From address invalid
To address valid
To data setup
To data hold
RCLK high
RCLK low
has reached 4.0 V (2.5 V for XC2000L).
CC
must rise from 2.0 V to V
Description
CC
may require a >1- s High level on RESET, followed by a >6- s Low level on RESET and
CC
has reached 4.0 V (2.5 V for XC2000L). A very long V
CC
min in less than 25 ms. If this is not possible, configuration can be de-
1
2
3
4
5
6
2-203
Symbol
6 T
T
T
T
T
T
T
ARC
RAC
DRC
RCD
RCH
RCL
RCL
1 T
ARC
3 T
Byte n + 1
DRC
Byte n - 1
D6
Min
600
4 T
4.0
60
5 T
0
RCD
2 T
RCH
RAC
CC
rise time of >100 ms, or
Max
200
D7
0
X5408
Units
ns
ns
ns
ns
ns
s