XC2018-70PC84C Xilinx Inc, XC2018-70PC84C Datasheet - Page 4

• Manufacturer Part Number: XC2018-70PC84C
• Description: IC LOGIC CL ARRAY 1800GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC2000r

Specifications of XC2018-70PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 17878
• Number Of I /o: 74
• Number Of Gates: 1500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 93+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1004

XC2000 Logic Cell Array Families
Figure 1. Logic Cell Array Structure
The static memory cell used for the configuration memory
in the Logic Cell Array has been designed specifically for
high reliability and noise immunity. Based on this design,
which has been patented, integrity of the LCA configura-
tion memory is assured even under adverse conditions.
Compared with other programming alternatives, static
memory provides the best combination of high density,
high performance, high reliability and comprehensive test-
ability. As shown in Figure 2, the basic memory cell
consists of two CMOS inverters plus a pass transistor used
for writing data to the cell. The cell is only written during
configuration and only read during readback. During nor-
mal operation the pass transistor is off and does not affect
the stability of the cell. This is quite different from the
normal operation of conventional memory devices, in
which the cells are continuously read and rewritten.
The outputs Q and Q control pass-transistor gates directly.
The absence of sense amplifiers and the output capacitive
load provide additional stability to the cell. Due to the
structure of the configuration memory cells, they are not
Configurable
Logic Block
2-188
Interconnect Area
I/O Block
affected by extreme power supply excursions or very high
levels of alpha particle radiation. In reliability testing no soft
errors have been observed, even in the presence of very
high doses of alpha radiation.
Input/Output Block
Each user-configurable I/O block (IOB) provides an inter-
face between the external package pin of the device and
the internal logic. Each I/O block includes a programmable
input path and a programmable output buffer. It also
provides input clamping diodes to provide protection from
electro-static damage, and circuits to protect the LCA from
latch-up due to input currents. Figure 3 shows the general
structure of the I/O block.
The input buffer portion of each I/O block provides thresh-
old detection to translate external signals applied to the
package pin to internal logic levels. The input buffer
threshold of the I/O blocks can be programmed to be
compatible with either TTL (1.4 V) or CMOS (2.2 V) levels.
The buffered input signal drives both the data input of an
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