XC2018-70PC84C Xilinx Inc, XC2018-70PC84C Datasheet - Page 30

• Manufacturer Part Number: XC2018-70PC84C
• Description: IC LOGIC CL ARRAY 1800GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC2000r

Specifications of XC2018-70PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 17878
• Number Of I /o: 74
• Number Of Gates: 1500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 93+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1004

XC2000 Logic Cell Array Families
Note: A PLCC in a “PGA-Footprint” socket has a different signal pinout than a PGA device.
MASTER-SET
M1 (LOW)
M0 (LOW)
M2 (LOW)
CCLK (O)
<0:0:0>
RCLK
<<HIGH>>
M1 (HIGH)
M0 (HIGH)
<<HIGH>>
<<HIGH>>
<<HIGH>>
CCLK (I)
<1:1:1>
SLAVE
DIN (I)
XC2064 Configuration Pin Assignments
Configuration Mode: <M2:M1:M0>
<<HIGH>> is high impedance with a 20-50 k internal pull-up during configuration
PERIPHERAL
PWRDWN (I)
HDC (HIGH)
LDC (LOW)
<<HIGH>>
<<HIGH>>
M0 (HIGH)
M2 (HIGH)
<<HIGH>>
<<HIGH>>
<<HIGH>>
M1 (LOW)
RESET (I)
DONE (O)
<1:0:1>
WRT (I)
CS0 (I)
CS1 (I)
CS2 (I)
GND
GND
VCC
CCLK (O)
DOUT (O)
Vcc
MASTER-HIGH
M1 (HIGH)
M0 (LOW)
<1:1:0>
2-214
A13
A12
A11
A10
A15
A14
A6
A7
A8
A9
A0
A1
A2
A3
A4
A5
RCLK
D7 (I)
D6 (I)
D5 (I)
D4 (I)
D3 (I)
D2 (I)
D1 (I)
D0 (I)
MASTER-LOW
(O)
(O)
(O)
(O)
(O)
(O)
(O)
(O)
(O)
(O)
(O)
(O)
(O)
(O)
(O)
(O)
M1 (LOW)
M0 (LOW)
<1:0:0>
PLCC
44
44
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
1
2
3
4
5
6
7
8
9
DIP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
48
1
2
3
4
5
6
7
8
9
PLCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
68
1
2
3
4
5
6
7
8
9
PGA
K10
K11
H10
H11
G10
G11
F10
F11
E10
E11
D10
D11
C10
C11
B11
B10
A10
L10
J10
J11
G2
G1
B6
A6
B5
A5
B4
A4
B3
A3
A2
B2
B1
C2
C1
D2
D1
E2
E1
F2
F1
H2
H1
K1
K2
K3
K4
K5
K6
K7
K8
K9
B9
A9
D8
A8
B7
A7
J2
J1
L2
L3
L4
L5
L6
L7
L8
L9
68
XTL2 OR I/O
XTL1 OR I/O
RDATA (O)
PWR DWN
Operation
RTRIG (I)
PROG (I)
CCLK (I)
RESET
GND
GND
User
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
X6103