XC2018-70PC84C Xilinx Inc, XC2018-70PC84C Datasheet - Page 9

• Manufacturer Part Number: XC2018-70PC84C
• Description: IC LOGIC CL ARRAY 1800GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC2000r

Specifications of XC2018-70PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 17878
• Number Of I /o: 74
• Number Of Gates: 1500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 93+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1004

interconnect fan-out and better performance. The repow-
ering buffers are bidirectional, since signals must be able
to propagate in either direction on a general interconnect
segment. Direction controls are automatically established
by the Logic Cell Array development system software.
Repowering buffers are provided only for the general-
purpose interconnect since the direct and Longline re-
sources do not exhibit the same R-C delay accumulation.
The Logic Cell Array is divided into nine sections with
buffers automatically provided for general interconnect at
the boundaries of these sections. These boundaries can
be viewed with the development system. For routing
within a section, no buffers are used. The delay calculator
of the XACT development system automatically calculates
and displays the block, interconnect and buffer delays for
any selected paths.
Longlines
Longlines, shown in Figure 8a, run both vertically and
horizontally the height or width of the interconnect area.
Each vertical interconnection column has two Longlines;
each horizontal row has one, with an additional Longline
adjacent to each set of I/O blocks. The Longlines bypass
the switch matrices and are intended primarily for signals
Figure 8a. Longline Interconnect
B
C
K
D
CLB
CLB
CLB
A
X
Y
Two Vertical
Long Lines
Switch
Switch
Matrix
Matrix
2-193
that must travel a long distance or must have minimum
skew among multiple destinations.
A global buffer in the Logic Cell Array is available to drive
a single signal to all B and K inputs of logic blocks. Using
the global buffer for a clock provides a very low skew, high
fan-out synchronized clock for use at any or all of the logic
blocks. At each block, a configuration bit for the K input to
the block can select this global line as the storage element
clock signal. Alternatively, other clock sources can be
used.
A second buffer below the bottom row of the array drives
a horizontal Longline which, in turn, can drive a vertical
Longline in each interconnection column. This alternate
buffer also has low skew and high fan-out capability. The
network formed by this alternate buffer’s Longlines can be
selected to drive the B, C or K inputs of the logic blocks.
Alternatively, these Longlines can be driven by a logic or
I/O block on a column by column basis. This capability
provides a common, low-skew clock or control line within
each column of logic blocks. Interconnections of these
Longlines are shown in Figure 8b.
Global
Long Lines
CLB
CLB
CLB
X5402
Horizontal
Long Lines