XC2018-70PC84C Xilinx Inc, XC2018-70PC84C Datasheet - Page 5

• Manufacturer Part Number: XC2018-70PC84C
• Description: IC LOGIC CL ARRAY 1800GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC2000r

Specifications of XC2018-70PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 17878
• Number Of I /o: 74
• Number Of Gates: 1500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 93+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1004

Figure 2. Configuration Memory Cell
Figure 3. I/O Block
edge-triggered D flip-flop and one input of a two-input
multiplexer. The output of the flip-flop provides the other
input to the multiplexer. The user can select either the
direct input path or the registered input, based on the
content of the memory cell controlling the multiplexer. The
I/O Blocks along each edge of the die share common
clocks. The flip-flops are reset during configuration as well
as by the active-low chip RESET input.
Output buffers in the I/O blocks provide 4-mA drive for high
fan-out CMOS or TTL-compatible signal levels. The output
data (driving I/O block pin O) is the data source for the I/O
Pin
Read or
Write
Data
=
D
Program-Controlled
Multiplexer
2-189
Q
Off
On
block output buffer. Each I/O block output buffer is con-
trolled by the contents of two configuration memory cells
which turn the buffer ON or OFF or select 3-state buffer
control. The user may also select the output buffer 3-state
control (I/O block pin TS). When this I/O block output
control signal is High (a logic one), the buffer is disabled
and the package pin is high-impedance.
Configurable Logic Block
An array of Configurable Logic Blocks (CLBs) provides the
functional elements from which the user’s logic is con-
structed. The logic blocks are arranged in a matrix in the
Q
Q
Configuration
Control
I/O Clock
X5382
TS (Output Enable)
Out
In
X5398