XC2018-70PC84C Xilinx Inc, XC2018-70PC84C Datasheet - Page 6

• Manufacturer Part Number: XC2018-70PC84C
• Description: IC LOGIC CL ARRAY 1800GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC2000r

Specifications of XC2018-70PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 17878
• Number Of I /o: 74
• Number Of Gates: 1500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 93+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1004

XC2000 Logic Cell Array Families
Figure 4. Configurable Logic Block
center of the device. The XC2064 has 64 such blocks
arranged in an 8-row by 8-column matrix. The XC2018 has
100 logic blocks arranged in a 10 by 10 matrix.
Each logic block has a combinatorial logic section, a
storage element, and an internal routing and control sec-
tion. Each CLB has four general-purpose inputs: A, B, C
and D; and a special clock input (K), which may be driven
from the interconnect adjacent to the block. Each CLB also
has two outputs, X and Y, which may drive interconnect
networks. Figure 4 shows the resources of a Configurable
Logic Block.
The logic block combinatorial logic uses a table look-up
memory to implement Boolean functions. This technique
can generate any logic function of up to four variables with
a high speed sixteen-bit memory. The propagation delay
through the combinatorial network is independent of
the function generated. Each block can perform any
function of four variables or any two functions of three
variables each. The variables may be selected from
among the four inputs and the block’s storage element
output Q. Figure 5 shows various options which may be
specified for the combinatorial logic.
If the single 4-variable configuration is selected (Option 1),
the F and G outputs are identical. If the 2-function alterna-
tive is selected (Option 2), logic functions F and G may be
independent functions of three variables each. The three
variables can be selected from among the four logic block
inputs and the storage element output Q. A third form of the
Inputs
A
B
C
D
Comb.
Logic
2-190
G
F
combinatorial logic (Option 3) is a special case of the 2-
function form in which the B input dynamically selects
between the two function tables providing a single merged
logic function output. This dynamic selection allows some
5-variable functions to be generated from the four block
inputs and storage element Q. Combinatorial functions are
restricted in that one may not use both its storage element
output Q and the input variable of the logic block pin “D” in
the same function.
If used, the storage element in each Configurable Logic
Block (Figure 6) can be programmed to be either an edge-
sensitive “D” type flip-flop or a level-sensitive “D” latch. The
clock or enable for each storage element can be selected
from:
•
•
•
The user may also select the clock active sense within
each logic block. This programmable inversion eliminates
the need to route both phases of a clock signal throughout
the device.
The storage element data input is supplied from the
function F output of the combinatorial logic. Asynchro-
nous SET and RESET controls are provided for each
storage element. The user may enable these controls
independently and select their source. They are active
High inputs and the asynchronous reset is dominant. The
Clock
The special-purpose clock input K
The general-purpose input C
The combinatorial function G
K
D
K
S
R
Q
Outputs
X
Y
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