XC2018-70PC84C Xilinx Inc, XC2018-70PC84C Datasheet - Page 24

• Manufacturer Part Number: XC2018-70PC84C
• Description: IC LOGIC CL ARRAY 1800GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC2000r

Specifications of XC2018-70PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 17878
• Number Of I /o: 74
• Number Of Gates: 1500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 93+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1004

General LCA Switching Characteristics
XC2000 Logic Cell Array Families
Notes: 1. At power-up, V
RESET
DONE/PROG
CLOCK
DONE/PROG
V
CC
PWRDWN
M0/M1/M2
USER I/O
(VALID)
CLOCK
RESET
2. RESET timing relative to power-on and valid mode lines (M0, M1, M2) is relevant only when RESET is used to
3. Minimum CLOCK widths for the auxillary buffer are 1.25 times the T
4. After RESET is High, RESET = D/P = Low for 6 s will abort to CLEAR.
(I/O)
2
delayed by holding RESET Low until V
ms, or a non-monotonically rising V
on RESET and D/P after V
delay configuration.
User State
M2, M1, M0 setup
M2, M1, M0 hold
Width—FF Reset
High before RESET
Device Reset
Progam width (Low)
Initialization
Device Reset
Clock (High)
Clock (Low)
CC
must rise from 2.0 V to V
2 T
Description
10 T
MR
VALID
CLH
CC
4
7 T
4
has reached (2.5 V for the XC2000L).
8 T
PGW
PGI
4
CC
may require a >1- s High level on RESET, followed by a >6- s Low level
CC
5 T
has reached (2.5 V for the XC2000L). A very long V
3 T
CC
RH
11 T
10
11
RM
min in less than 25 ms. If this is not possible, configuration can be
2
3
4
5
6
7
8
9
Symbol
Initialization State
CLL
2-208
T
T
T
T
T
T
T
T
T
T
MR
RM
MRW
RH
DRRW
PGW
PGI
DRDW
CLH
CLL
6 T
9 T
12 T
DRRW
DRDW
PS
CLH
, T
CLL
150
Min
.
60
60
6
6
6
6
8
8
V
CC
PD
13 T
rise time of >100
Max
PH
7
4 T
MRW
X5386
Units
ns
ns
ns
ns
ns
s
s
s
s
s