XC2018-70PC84C Xilinx Inc, XC2018-70PC84C Datasheet - Page 3

• Manufacturer Part Number: XC2018-70PC84C
• Description: IC LOGIC CL ARRAY 1800GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC2000r

Specifications of XC2018-70PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 17878
• Number Of I /o: 74
• Number Of Gates: 1500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 93+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1004

Features
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Description
The Logic Cell Array (LCA) is a high density CMOS
integrated circuit. Its user-programmable array architec-
ture is made up of three types of configurable elements:
Input/Output Blocks, logic blocks and Interconnect. The
designer can define individual I/O blocks for interface to
external circuitry, define logic blocks to implement logic
functions and define interconnection networks to compose
larger scale logic functions. The XACT Development Sys-
tem provides interactive graphic design capture and auto-
matic routing. Both logic simulation and in-circuit emula-
tion are available for design verification.
The Logic Cell Array is available in a variety of logic
capacities, package styles, temperature ranges and speed
grades.
Fully Field-Programmable:
– I/O functions
– Digital logic functions
– Interconnections
General-purpose array architecture
Complete user control of design cycle
Compatible arrays with logic cell complexity equiva-
lent from 600 to 1,500 gates
Available in 5-V and 3.3-V versions
100% factory tested
Selectable configuration modes
Low-power, CMOS, static-memory technology
Performance equivalent to TTL SSI/MSI
TTL or CMOS input thresholds
Complete development system support
– XACT Design Editor
– Schematic Entry
– Macro Library
– Timing Calculator
– Logic and Timing Simulator
– Auto Place / Route
2-187
XC2000
Logic Cell Array Families
Product Description
Device
XC2064
XC2064L 3.3 V
XC2018
XC2018L 3.3 V
The XC2000 family operates with a nominal 5.0 V supply.
The XC2000L family operates with nominal 3.3 V supply.
The LCA logic functions and interconnections are deter-
mined by data stored in internal static-memory cells. On-
chip logic provides for automatic loading of configuration
data at power-up. The program data can reside in an
EEPROM, EPROM or ROM on the circuit board or on a
floppy disk or hard disk. The program can be loaded in a
number of modes to accommodate various system re-
quirements.
Architecture
The general structure of a Logic Cell Array is shown in
Figure 1. The elements of the array include three catego-
ries of user programmable elements: I/O Blocks (IOBs),
Configurable Logic Blocks (CLBs) and Programmable
Interconnections. The I/OBs provide an interface between
the logic array and the device package pins. The CLBs
perform user-specified logic functions, and the intercon-
nect resources are programmed to form networks that
carry logic signals among the blocks.
LCA configuration is established through a distributed
array of memory cells.The XACT development system
generates the program used to configure the Logic Cell
Array which includes logic to implement automatic con-
figuration.
Configuration Memory
The configuration of the Logic Cell Array is established by
programming memory cells which determine the logic
functions and interconnections. The memory loading pro-
cess is independent of the user logic functions.
5.0 V
5.0 V
V
CC
1,000 - 1,500
1,000 - 1,500
600 – 1,000
600 – 1,000
Typ. Logic
Capacity
(gates)
CLBs
100
100
64
64
User
I/O
Max
58
58
74
74
12,038
12,038
17,878
17,878
Config.
bits