XC5VLX50T-1FFG1136CES Xilinx Inc, XC5VLX50T-1FFG1136CES Datasheet - Page 100
![IC FPGA VIRTEX-5 ES 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-1FFG1136CES
Manufacturer Part Number
XC5VLX50T-1FFG1136CES
Description
IC FPGA VIRTEX-5 ES 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FFG1136CES
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VLX50T-1FFG1136CES
Manufacturer:
Xilinx Inc
Quantity:
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Chapter 3: Phase-Locked Loops (PLLs)
100
PLL CLKIN1 and CLKIN2 Usage
CLKIN1 is the general purpose input to the PLL. The CLKIN2 pin is used to dynamically
switch between CLKIN1 and CLKIN2 during operation, as selected by the CLKINSEL pin.
If both CLKIN1 and CLKIN2 are used, and the PLL input clocks are driven by global clock
pins, there are several restrictions on the placement of both clock signal pins. CLKIN1 can
only come from IBUFG[4-0]. CLKIN2 can only come from IBUFG[9-5]. Further, CLKIN2
has to be mapped to a specific location depending on the value of CLKIN1. These rules are
as follows:
If CLKIN1 is connected to IBUFG [x], CLKIN2 needs to be IBUFG [y] of the same type.
Table 3-5
Table 3-5: Mapping Locations
When the PLL input clocks are driven by the global clock trees (BUFGs), both clock inputs
must be connected to the same clock input type. Driving one PLL clock input with a IBUFG
and the other with a BUFG is not possible.
The following tables map the Virtex-5 FPGA global clock IBUFG pins with respect to
CLKIN1 and CLKIN2. PLLs in the top half of the Virtex-5 device are driven by the global
clock pins in bank3 and can be paired as listed in
Table 3-6: PLLs in the Top Half Pairing
IO_L9P_GC_3
IO_L8P_GC_3
IO_L7P_GC_3
IO_L6P_GC_3
IO_L5P_GC_3
CLKIN1
CLKIN1
[0]
[1]
[2]
[3]
[4]
shows the general clock pin pairing.
CLKIN2
[5]
[6]
[7]
[8]
[9]
www.xilinx.com
IO_L4P_GC_3
IO_L3P_GC_3
IO_L2P_GC_3
IO_L1P_GC_3
IO_L0P_GC_3
CLKIN2
Table
3-6.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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