XC5VLX50T-1FFG1136CES Xilinx Inc, XC5VLX50T-1FFG1136CES Datasheet - Page 295
![IC FPGA VIRTEX-5 ES 50K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50T-1FFG1136CES
Manufacturer Part Number
XC5VLX50T-1FFG1136CES
Description
IC FPGA VIRTEX-5 ES 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50T-1FFG1136CES
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
2211840
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50T-1FFG1136CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Transmitter Termination
Receiver Termination
The Virtex-5 FPGA LVDS transmitter does not require any external termination.
lists the allowed attributes corresponding to the Virtex-5 FPGA LVDS current-mode
drivers. Virtex-5 FPGA LVDS current-mode drivers are a true current source and produce
the proper (EIA/TIA compliant) LVDS signal.
Figure 6-87
50 Ω transmission lines.
X-Ref Target - Figure 6-87
Figure 6-88
50 Ω transmission lines.
X-Ref Target - Figure 6-88
Table 6-36
Table 6-36: Allowed Attributes of the LVDS I/O Standard
IOSTANDARD
DIFF_TERM
Attributes
LVDS_25
External Termination
lists the available Virtex-5 FPGA LVDS I/O standards and attributes supported.
is an example of a differential termination for an LVDS receiver on a board with
is an example of differential termination for an LVDS receiver on a board with
Figure 6-88: LVDS_25 With DIFF_TERM Receiver Termination
LVDS_25
IOB
Figure 6-87: LVDS_25 Receiver Termination
www.xilinx.com
IOB
IBUFDS/IBUFGDS
0
TRUE, FALSE
Z
Z
0
0
R DIFF = 2Z 0 = 100Ω
= 50Ω
= 50Ω
Specific Guidelines for I/O Supported Standards
0
Z 0
Z 0
LVDS_25, LVDSEXT_25
Primitives
IOB
R DIFF = 100Ω
IOB
OBUFDS/OBUFTDS
+
–
N/A
LVDS_25
LVDS_25
+
–
ug190_6_81_030506
ug190_6_82_030506
Data in
Table 6-36
295
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